Patents by Inventor Cheng-Tien Wan

Cheng-Tien Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9559099
    Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9450098
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20150380527
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9153582
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20150162447
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 8994002
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20140284726
    Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.
    Type: Application
    Filed: June 3, 2014
    Publication date: September 25, 2014
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 8815712
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20140220753
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 7, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 8742509
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20130240836
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20130228875
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20130171792
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Application
    Filed: March 7, 2012
    Publication date: July 4, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann