Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A water quality sensor includes a housing including a light transmissive bucket mounted in an electrical washing appliance and a light transmissive inner barrel mounted in the bucket, an actuation module mounted in the inner barrel for detecting a water quality of a washing solution in the electrical washing appliance. Thus, if the bucket is cracked during manufacturing or due to a collision, the actuation module can still be well protected by the inner barrel, so that the washing solution in the electrical washing machine does not directly flow into and contact with the actuation module to cause an accidental short circuit of the circuit substrate of the actuation module, improving the water resistance and service life of the water quality sensor.

Abstract: A water quality sensor includes a housing including a light transmissive bucket mounted in an electrical washing appliance and a light transmissive inner barrel mounted in the bucket, an actuation module mounted in the inner barrel for detecting a water quality of a washing solution in the electrical washing appliance. Thus, if the bucket is cracked during manufacturing or due to a collision, the contact actuation module can still be well protected by the inner barrel, so that the washing solution in the electrical washing machine does not directly flow into contact with the actuation module to cause an accidental short circuit of the circuit substrate of the actuation module, improving the water resistance and service life of the water quality sensor.

Abstract: A water quality sensor includes a housing including a light transmissive bucket mounted in an electrical washing appliance and a light transmissive inner barrel mounted in the bucket, an actuation module mounted in the inner barrel for detecting a water quality of a washing solution in the electrical washing appliance. Thus, if the bucket is cracked during manufacturing or due to a collision, the contact actuation module can still be well protected by the inner barrel, so that the washing solution in the electrical washing machine does not directly flow into contact with the actuation module to cause an accidental short circuit of the circuit substrate of the actuation module, improving the water resistance and service life of the water quality sensor.

Abstract: A water quality sensor includes a housing including a light transmissive bucket mounted in an electrical washing appliance and a light transmissive inner barrel mounted in the bucket, an actuation module mounted in the inner barrel for detecting a water quality of a washing solution in the electrical washing appliance. Thus, if the bucket is cracked during manufacturing or due to a collision, the actuation module can still be well protected by the inner barrel, so that the washing solution in the electrical washing machine does not directly flow into and contact with the actuation module to cause an accidental short circuit of the circuit substrate of the actuation module, improving the water resistance and service life of the water quality sensor.

Abstract: An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.

Abstract: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: An apparatus for signal detection to enhance performance of a receiver and method therefor. The signal detection unit provides at least three filtered output signals with different bandwidths, wherein at least one of output signals is generated by phase derotation and filtering. The three filtered digital signals are provided for a subsequent stage, such as a digital signal processor, to perform further operations of a receiver in different modes, such as a synchronization mode where the receiver synchronizes with a base station or a normal mode where transmitted data contained in the received signal is extracted. The signal detection unit includes a memory buffer with a reduced memory size for preparation of the three filtered digital signals efficiently. The circuit complexity and size can be dramatically improved and the performance of the receiver can be enhanced by the signal detection unit.

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.

Abstract: A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the end of each leads. The chip is disposed on the top surface of the die pad and is electrically connected to the leads. The molding compound encapsulates the chip, a portion of the leads and the die pad, and fills the gaps between the leads.

Abstract: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

Abstract: The present invention relates to an audio data synthesis system for sequentially processing a first predetermined number of audio data to synthesize a digital audio signal cumulatively. The system comprises a first memory, a first processor, an audio data processing unit, and a second memory. The first memory is for storing a plurality of audio data. The first processor is for generating an audio processing request for requesting to process a second predetermined number of audio data. The audio data processing unit is for receiving the audio processing request, accessing the second predetermined number of audio data stored in the first memory, and calculating every two neighboring audio data to get data processing values, and after calculating all the second predetermined number of audio data, then obtaining a third predetermined number of data processing values. The second memory is for storing the third predetermined number of audio data.