Patents by Inventor Cheng-Tsung WU

Cheng-Tsung WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200308451
    Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) about 0.05 wt. % to about 10 wt. % of an abrasive; (b) a dispersant, wherein the dispersant is a linear or branched C2-C10 alkylenediol; and (c) water, wherein the chemical-mechanical polishing composition has a pH of about 2 to about 6. The invention also provides a method of chemically-mechanically polishing a substrate by contacting the substrate with the inventive chemical-mechanical polishing composition.
    Type: Application
    Filed: March 23, 2020
    Publication date: October 1, 2020
    Inventors: Yang-Yao LEE, Hsin-Yen WU, Cheng-Yuan KO, Lung-Tai LU, Hung-Tsung HUANG
  • Publication number: 20200251449
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Patent number: 10724140
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Publication number: 20200227342
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 16, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Hsiao-Ling CHIANG, Wen-Hsin LIN
  • Patent number: 10714410
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Hsiao-Ling Chiang, Wen-Hsin Lin
  • Publication number: 20200194321
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 18, 2020
    Applicant: United Microelectronics Corp.
    Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Publication number: 20190378714
    Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Cheng-Tsung WU, Po-Hsiung LEU, Ding-I LIU, Si-Wen LIAO, Hsiang-Sheng KUNG
  • Patent number: 10395918
    Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Tsung Wu, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Hsiang-Sheng Kung
  • Publication number: 20190222211
    Abstract: This disclosure presents a power switching module combining a novel gate driver with a photonic isolated power source which can output a high voltage and high power at the same time, and thus can drive a power semiconductor device. The disclosed power switching module could simplify the switched mode power supply structure to (1) replace the isolated power supply module; (2) simplify circuitry of the gate driver by integrating gate driver signaling opto-electronics; and (3) provide a module with power semiconductor device under switched mode power supply structure.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Inventors: Mei-huan Yang, Cheng-liang Wu, Remigio Perales, Kun-hsien Chen, Wei-sheng Chao, Ying-lin Tseng, I-tsung Chen
  • Patent number: 10297943
    Abstract: An electrical receptacle connector includes a plurality of first terminals, a plurality of second terminals, a first insulator, a second insulator, a shielding plate and a third insulator. The first insulator includes a first front insulating portion and a first rear insulating portion. The first front insulating portion covers a part of each of the first terminals. The second rear insulating portion covers another part of each of the first terminals. The second insulator partially covers each of the second terminals. The third insulator partially covers each of the first terminals, the second terminals, the first insulator, the second insulator and the shielding plate.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 21, 2019
    Assignee: Advanced Connectek Inc.
    Inventors: Pin-Yuan Hou, Yu-Lun Tsai, Long-Fei Chen, Kang Qin Li, Hsu-Fen Wang, Chien-Tsung Chuang, Cheng-Yan Wu
  • Publication number: 20190146349
    Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer having a plurality of exposure fields over a wafer stage. The method further includes projecting an extreme ultraviolet (EUV) light over the semiconductor wafer. The method also includes securing the semiconductor wafer to the wafer stage by applying a first adjusted voltage to an electrode of the wafer stage while the EUV light is projected to a first group of the exposure fields of the semiconductor wafer. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.
    Type: Application
    Filed: June 27, 2018
    Publication date: May 16, 2019
    Inventors: Cheng-Kuan WU, Po-Chung CHENG, Li-Jui CHEN, Chih-Tsung SHIH
  • Patent number: 10262938
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10256340
    Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region having a second conductivity type therein. An epitaxial layer is on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer on the first doping region. A second doping region and a third doping region that have the second conductivity type are respectively in the epitaxial layer on both opposite sides of the body region, so as to adjoin the body region. Source and drain regions are respectively in the body region and the second doping region. A field insulating layer is in the second doping region between the source and drain regions. A gate structure is on the epitaxial layer to cover a portion of the field insulating layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Publication number: 20190081042
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
  • Patent number: 10229907
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Publication number: 20190067190
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 10181512
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Publication number: 20190006355
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
  • Patent number: 10170468
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Patent number: 10161041
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu