Patents by Inventor Cheng-Tsung WU

Cheng-Tsung WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190378714
    Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Cheng-Tsung WU, Po-Hsiung LEU, Ding-I LIU, Si-Wen LIAO, Hsiang-Sheng KUNG
  • Patent number: 10475784
    Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Hao Ho, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Publication number: 20190267455
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Yu-Hao HO, Shin-Cheng LIN, Cheng-Tsung WU
  • Patent number: 10395918
    Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Tsung Wu, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Hsiang-Sheng Kung
  • Patent number: 10262938
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10256340
    Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region having a second conductivity type therein. An epitaxial layer is on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer on the first doping region. A second doping region and a third doping region that have the second conductivity type are respectively in the epitaxial layer on both opposite sides of the body region, so as to adjoin the body region. Source and drain regions are respectively in the body region and the second doping region. A field insulating layer is in the second doping region between the source and drain regions. A gate structure is on the epitaxial layer to cover a portion of the field insulating layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Lung Chin, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Publication number: 20190081042
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
  • Patent number: 10229907
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Publication number: 20190067190
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 10181512
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Publication number: 20190006355
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
  • Patent number: 10170468
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Patent number: 10161041
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Publication number: 20180350799
    Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Hao HO, Shin-Cheng LIN, Wen-Hsin LIN, Cheng-Tsung WU
  • Publication number: 20180334747
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Patent number: 10128331
    Abstract: A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 13, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Publication number: 20180308934
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Application
    Filed: January 10, 2018
    Publication date: October 25, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
  • Publication number: 20180203523
    Abstract: An information display method for a computer having a keyboard. The method includes selecting a first system information among a plurality of system information, wherein the system information is configured to respectively indicate statuses of a plurality of devices of the computer; selecting a first display pattern among a plurality of display patterns according to the first system information; selecting a first keyboard region for applying the first display pattern; and showing the first system information in real-time by a plurality of first buttons corresponding to the first keyboard region of the keyboard according to the selected first display pattern, the first keyboard region and the first system information.
    Type: Application
    Filed: November 3, 2017
    Publication date: July 19, 2018
    Applicant: Acer Incorporated
    Inventors: Yu-Chuan Cheng, Ling-Fan Tsao, Cheng-Tsung Wu
  • Patent number: 10014408
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 3, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin, Cheng-Tsung Wu, Manoj Kumar
  • Patent number: 9941356
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 10, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho