Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: The present invention provides a method of manufacturing a transistor with a footed offset spacer is disclosed. The method comprises providing a substrate. The gate structure is formed on the substrate and an insulating layer is then formed on the substrate and the gate structure. A portion of said insulating layer is removed by a method of anisotropic dry etching to form the footed offset spacer at a side-wall of the gate structure, wherein the footed offset spacer is formed by adjusting a first flow rate of a first gas and a second flow rate of a second flow gas in the anisotropic dry etching. The footed offset spacer can improve time delay of the propagation and power dissipation.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer.