Patents by Inventor Cheng Tung Lin
Cheng Tung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940388Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).Type: GrantFiled: March 16, 2018Date of Patent: March 26, 2024Assignee: IXENSOR CO., LTD.Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
-
Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
-
Publication number: 20220367667Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Patent number: 11444028Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
-
Patent number: 11411094Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: GrantFiled: January 13, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Patent number: 11227788Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.Type: GrantFiled: July 6, 2020Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
-
Patent number: 11056486Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.Type: GrantFiled: March 28, 2019Date of Patent: July 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Hui-Cheng Chang
-
Publication number: 20210050430Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: ApplicationFiled: November 4, 2020Publication date: February 18, 2021Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
-
Patent number: 10854728Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: December 9, 2019Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
-
Publication number: 20200335388Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
-
Patent number: 10707114Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.Type: GrantFiled: July 30, 2018Date of Patent: July 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
-
Patent number: 10658234Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.Type: GrantFiled: July 29, 2016Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Hsiu Hung, Sung-Li Wang, Pei-Wen Wu, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi-On Chui
-
Publication number: 20200152763Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Publication number: 20200118935Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
-
Publication number: 20200111887Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
-
Patent number: 10535748Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: GrantFiled: March 1, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Patent number: 10510664Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: August 14, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
-
Patent number: 10505014Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: March 29, 2017Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
-
Patent number: 10418271Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.Type: GrantFiled: June 13, 2014Date of Patent: September 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Cheng-Tung Lin, Chih-Tang Peng, Chien-Hsun Wang, Bing-Hung Chen, Huan-Just Lin, Yung-Cheng Lu
-
Publication number: 20190273147Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wen CHENG, Cheng-Tung LIN, Chih-Wei CHANG, Hong-Mao LEE, Ming-Hsing TSAI, Sheng-Hsuan LIN, Wei-Jung LIN, Yan-Ming TSAI, Yu-Shiuan WANG, Hung-Hsu CHEN, Wei-Yip LOH, Ya-Yi CHENG