Patents by Inventor Cheng Tung Lin
Cheng Tung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140264362Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.Type: ApplicationFiled: May 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Kuo-Yin Lin, Wan-Chun Pan, Ming-Liang Yen, Huicheng Chang
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Publication number: 20140273412Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.Type: ApplicationFiled: June 21, 2013Publication date: September 18, 2014Inventors: Li-Lan Wu, Chi-Yuan Chen, Ming-Chyi Liu, Cary Chia-Chiung Lo, Teng-Chun Tsai, Cheng-Tung Lin, Kuo-Yin Lin, Li-Ting Wang, Wan-Chun Pan, Ming-Liang Yen, Huicheng Chang
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Patent number: 8822293Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.Type: GrantFiled: March 13, 2008Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yihang Chiu, Shu-Tine Yang, Jyh-Cherng Sheu, Chu-Yun Fu, Cheng-Tung Lin
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Patent number: 8723275Abstract: A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.Type: GrantFiled: January 27, 2009Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Jung Lin, Cheng-Tung Lin, Chih-Wei Chang, Shau-Lin Shue
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Patent number: 8304841Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.Type: GrantFiled: April 16, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeff J. Xu, Cheng-Tung Lin, Hsiang-Yi Wang, Wen-Chin Lee, Betty Hsieh
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Patent number: 8198685Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.Type: GrantFiled: December 23, 2008Date of Patent: June 12, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Shi Liu, Yung-Sheng Chiu, Cheng-Tung Lin, Chen-Hua Yu
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Patent number: 8138076Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.Type: GrantFiled: May 12, 2008Date of Patent: March 20, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Tung Lin, Yung-Sheng Chiu, Hsiang-Yi Wang, Chia-Lin Yu, Chen-Hua Yu
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Publication number: 20110178171Abstract: A method of inhibiting the cellular proliferation of at least one selected from the group consisting of androgen dependent prostate cancer cells, androgen independent prostate cancer cells, oral cancer cells, liver cancer cells (hepatoma), and gastric cancer cells in a subject is provided, wherein the method comprises administrating to the subject an effective amount of an active component selected from the group consisting of Z form isochaihulactone (Z-K8) of the following formula (I), E form isochaihulactone (E-K8) of the following formula (II), a pharmaceutically acceptable salt of Z-K8 or E-K8, a pharmaceutically acceptable ester of Z-K8 or E-K8, and combinations thereof: and R is H, alkoxy, or aryl. Also provided is a method for manufacturing Z-K8 and E-K8.Type: ApplicationFiled: January 18, 2011Publication date: July 21, 2011Applicant: China Medical UniversityInventors: Yi-Lin CHEN, Horng-Jyh Harn, Shinn-Zong Lin, Tzyy-Wen Chiou, Cheng-Tung Lin
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Patent number: 7977772Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: GrantFiled: May 11, 2010Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
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Patent number: 7947588Abstract: A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.Type: GrantFiled: April 15, 2009Date of Patent: May 24, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Hsiang-Yi Wang, Yung-Sheng Chiu, Chia-Lin Yu
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Publication number: 20110062526Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.Type: ApplicationFiled: April 16, 2010Publication date: March 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeff J. XU, Cheng-Tung LIN, Hsiang-Yi WANG, Wen-Chin LEE, Betty HSIEH
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Patent number: 7892961Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.Type: GrantFiled: May 31, 2007Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Liang-Gi Yao
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Patent number: 7799628Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.Type: GrantFiled: January 15, 2009Date of Patent: September 21, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Hsiang-Yi Wang, Cheng-Tung Lin, Chen-Hua Yu
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Publication number: 20100221878Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: ApplicationFiled: May 11, 2010Publication date: September 2, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
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Patent number: 7745890Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: GrantFiled: September 28, 2007Date of Patent: June 29, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
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Publication number: 20100155849Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: TAIWAN SEMICONDUTOR MANUFACTURING CO., LTD.Inventors: Chung-Shi LIU, Yung-Sheng Chiu, Cheng-Tung Lin, Chen-Hua Yu
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Publication number: 20100151639Abstract: Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shau-Lin Shue, Chen-Hua Yu, Cheng-Tung Lin, Chii-Ming Wu, Shih-Wei Chou, Gin Jei Wang, CP Lo, Chih-Wei Chang
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Publication number: 20100084718Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.Type: ApplicationFiled: January 15, 2009Publication date: April 8, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shi LIU, Hsiang-Yi WANG, Cheng-Tung LIN, Chen-Hua YU
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Publication number: 20100052066Abstract: A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.Type: ApplicationFiled: April 15, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Hsiang-Yi Wang, Yung-Sheng Chiu, Chia-Lin Yu
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Patent number: 7629655Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.Type: GrantFiled: March 20, 2007Date of Patent: December 8, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Chen-Nan Yeh