Abstract: A silicon carbide semiconductor device comprises a silicon carbide substrate, a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a plurality of trenches and a gate electrode. The first doped regions are disposed in the drift layer and form a plurality of first p-n junctions and a plurality of JFET regions with the drift layer. The second doped regions are disposed within the first doped regions and form a plurality of second p-n junctions with the first doped regions. The third doped regions are disposed in the first doped regions and adjacent to the second doped regions. The trenches penetrate into the drift layer and run horizontally through the JFET regions. The gate electrode is disposed over a main surface and in the trenches, which is electrically isolated from the drift layer by a gate insulating layer.

Abstract: A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (Wg) which is satisfied the following formula: Wg>Wjfet+2×Lch+2×Lx Lch represents a channel length of channel regions, Wjfet represents a minimum width of JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region.

Abstract: A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.

Abstract: A silicon carbide semiconductor device comprises a drift layer, a plurality of transistor cells and a gate structure. Each of the transistor cells comprises a first doped region, a second doped region, a third doped region and a fourth doped region. The first doped region is disposed in the drift layer. The second doped region is disposed in the first doped region. The third doped region is disposed in the first doped region and adjacent to the second doped region. The fourth doped region is disposed in or on the first doped region to form a channel region and is configured in a way such that the channel region is not fully depleted when a driving gate voltage applied to the semiconductor device is zero and the channel region is fully depleted when the driving gate voltage is less than a negative threshold voltage.

Abstract: A silicon carbide semiconductor device has an active area, a termination area surrounding the active area in a plan view. The silicon carbide semiconductor device comprises a SiC substrate, a drift layer, an insulating layer, a polysilicon layer, an interlayer dielectric layer disposed on the polysilicon layer, and a metal layer. The polysilicon layer includes a first portion disposed over the active area and a second portion disposed over the termination area. The metal layer includes a first portion disposed over the active area and a second portion disposed over the termination area. At least one of the second portion of the polysilicon layer and the second portion of the metal layer is configurated to electrically connect to at least one of a gate electrode and a source electrode.

Abstract: A silicon carbide semiconductor device comprises a SiC substrate, a drift layer disposed on the substrate, a plurality of first doping regions formed near a surface of the drift layer, a plurality of second doping regions formed near the surface of the drift layer and between the first doping regions and a first metal layer disposed on the surface of the drift layer. The first metal layer forms an Ohmic contact with the second doped region. The drift layer has a first doping concentration of a first conductivity type and each of the second doping regions has a second doping concentration of the first conductivity type, which is higher than the first doping concentration. Each of the first doping regions has a first depth and each of the second doping regions has a second depth which is smaller than the first depth.

Abstract: A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (Wg) which is satisfied the following formula: Wg>Wjfet+2×Lch+2×Lx Lch represents a channel length of channel regions, Wjfet represents a minimum width of JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region.

Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Abstract: The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

Abstract: A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing.

Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or fed back from the power transistor device; wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or feedbacked from the power transistor device: wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

Abstract: A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.

Abstract: A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.

Abstract: A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing.

Abstract: The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

Abstract: A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.

Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

Abstract: The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.