Patents by Inventor Cheng-Tyng Yen
Cheng-Tyng Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10396774Abstract: An intelligent power component module operable to be driven by a negative gate voltage integrates a wide bandgap semiconductor power unit, an adjustment unit and a driving unit so as to adjust a voltage level of the driving unit by the adjustment unit. Accordingly, the wide bandgap semiconductor power unit, in a driven state, comprises a driving voltage level alternating between a positive and a negative voltage.Type: GrantFiled: September 14, 2017Date of Patent: August 27, 2019Assignee: Hestia Power Inc.Inventors: Chien-Chung Hung, Fu-Jen Hsu, Cheng-Tyng Yen, Chwan-Ying Lee
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Publication number: 20190181849Abstract: An intelligent power component module operable to be driven by a negative gate voltage integrates a wide bandgap semiconductor power unit, an adjustment unit and a driving unit so as to adjust a voltage level of the driving unit by the adjustment unit. Accordingly, the wide bandgap semiconductor power unit, in a driven state, comprises a driving voltage level alternating between a positive and a negative voltage.Type: ApplicationFiled: September 14, 2017Publication date: June 13, 2019Inventors: Chien-Chung Hung, Fu-Jen Hsu, Cheng-Tyng Yen, Chwan-Ying Lee
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Publication number: 20190081136Abstract: A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.Type: ApplicationFiled: September 8, 2017Publication date: March 14, 2019Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
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Patent number: 10020368Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.Type: GrantFiled: November 30, 2016Date of Patent: July 10, 2018Assignee: HESTIA POWER INC.Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Hsiang-Ting Hung, Yao-Feng Huang, Chwan-Ying Lee
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Patent number: 9761703Abstract: A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.Type: GrantFiled: July 12, 2016Date of Patent: September 12, 2017Assignee: HESTIA POWER INC.Inventors: Fu-Jen Hsu, Chien-Chung Hung, Yao-Feng Huang, Cheng-Tyng Yen, Chwan-Ying Lee
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Publication number: 20170250275Abstract: The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.Type: ApplicationFiled: May 16, 2017Publication date: August 31, 2017Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
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Publication number: 20170207305Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.Type: ApplicationFiled: November 30, 2016Publication date: July 20, 2017Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Hsiang-Ting Hung, Yao-Feng Huang, Chwan-Ying Lee
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Patent number: 9685552Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.Type: GrantFiled: January 7, 2015Date of Patent: June 20, 2017Assignee: Hestia Power Inc.Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Hsiang-Ting Hung, Chwan-Ying Lee
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Patent number: 9645204Abstract: A magnetic sensor for sensing an external magnetic field includes first and second electrodes and first and second magnetic tunneling junctions. The first and second electrodes are disposed over a substrate; and the first and second magnetic tunneling junctions are conductively disposed between the first and second electrodes and connected in parallel between the first and second electrodes. The first and second magnetic tunneling junctions are arranged along a first easy axis of the magnetic sensor. The first magnetic tunneling junction includes a first pinned magnetization and a first free magnetization, and the second magnetic tunneling junction includes a second pinned magnetization and a second free magnetization. The first free magnetization and the second free magnetization are arranged substantially in parallel to the first easy axis and in substantially opposite directions.Type: GrantFiled: December 20, 2012Date of Patent: May 9, 2017Assignee: Industrial Technology Research InstituteInventors: Young-Shying Chen, Cheng-Tyng Yen
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Patent number: 9625538Abstract: A circuit for sensing an external magnetic field includes first voltage source, first magnetic sensor, second magnetic sensor, bias voltage unit, clamp voltage current mirror unit, signal transfer amplifying unit. The first voltage source provides a power voltage. The first magnetic sensor provides a reference current. The second magnetic sensor senses an external magnetic field and the conductivity of the second magnetic sensor varies in response to the external magnetic field. The bias voltage unit connected to the first magnetic sensor and the second magnetic sensor provides a bias voltage to the first magnetic sensor and the second magnetic sensor. The clamp voltage current mirror unit generates a reference current for the first magnetic sensor and mirrors the reference current to the second magnetic sensor. The signal transfer amplifying unit generates an output voltage and an additional current to compensate the change in the conductivity of the second magnetic sensor.Type: GrantFiled: June 27, 2016Date of Patent: April 18, 2017Assignee: Industrial Technology Research InstituteInventors: Young-Shying Chen, Cheng-Tyng Yen
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Publication number: 20160306017Abstract: A circuit for sensing an external magnetic field includes first voltage source, first magnetic sensor, second magnetic sensor, bias voltage unit, clamp voltage current mirror unit, signal transfer amplifying unit. The first voltage source provides a power voltage. The first magnetic sensor provides a reference current. The second magnetic sensor senses an external magnetic field and the conductivity of the second magnetic sensor varies in response to the external magnetic field. The bias voltage unit connected to the first magnetic sensor and the second magnetic sensor provides a bias voltage to the first magnetic sensor and the second magnetic sensor. The clamp voltage current mirror unit generates a reference current for the first magnetic sensor and mirrors the reference current to the second magnetic sensor. The signal transfer amplifying unit generates an output voltage and an additional current to compensate the change in the conductivity of the second magnetic sensor.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Young-Shying Chen, Cheng-Tyng Yen
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Patent number: 9373713Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.Type: GrantFiled: February 3, 2015Date of Patent: June 21, 2016Assignee: HESTIA POWER INC.Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Yao-Feng Huang, Hsiang-Ting Hung, Chwan-Ying Lee
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Patent number: 9368650Abstract: A SiC junction barrier controlled Schottky rectifier includes a SiC substrate, a n-type drift layer, a p-type doping region, a plurality of junction field-effect regions, a first metal layer and a second metal layer. The drift layer is disposed on the SiC substrate. The junction field-effect regions are disposed in the drift layer and are surrounded by the p-type doping region. The first metal layer is disposed on the drift layer. The second metal layer is disposed at one side of the SiC substrate away from the drift layer. Through N circular regions and (N?1) inter-circle regions each connecting two of the circular regions, as well as geometric characteristics of the circular regions and the inter-circle regions, a leakage current of devices is effectively reduced and ruggedness is increased to improve an issue of a large leakage current of a conventional Schottky barrier diode.Type: GrantFiled: July 16, 2015Date of Patent: June 14, 2016Assignee: HESTIA POWER INC.Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
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Publication number: 20160141412Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.Type: ApplicationFiled: February 3, 2015Publication date: May 19, 2016Inventors: Cheng-Tyng YEN, Chien-Chung HUNG, Yao-Feng HUANG, Hsiang-Ting HUNG, Chwan-Ying LEE
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Publication number: 20160126346Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.Type: ApplicationFiled: January 7, 2015Publication date: May 5, 2016Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Hsiang-Ting Hung, Chwan-Ying Lee
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Publication number: 20160111533Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.Type: ApplicationFiled: December 14, 2015Publication date: April 21, 2016Inventors: Cheng-Tyng YEN, Chien-Chung HUNG, Chwan-Ying LEE, Lurng-Shehng LEE
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Patent number: 9246016Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.Type: GrantFiled: March 25, 2015Date of Patent: January 26, 2016Assignee: HESTIA POWER INC.Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
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Publication number: 20160005883Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.Type: ApplicationFiled: March 25, 2015Publication date: January 7, 2016Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
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Patent number: 9209293Abstract: Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.Type: GrantFiled: April 18, 2013Date of Patent: December 8, 2015Assignee: Industrial Technology Research InstituteInventors: Chien-Chung Hung, Young-Shying Chen, Cheng-Tyng Yen, Chwan-Ying Lee
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Publication number: 20150287818Abstract: A semiconductor structure comprising a substrate, a drift layer, at least a doping region, an epitaxial channel, a gate oxide layer, a gate metal and an isolation layer is provided. The drift layer is disposed on the substrate. The doping region comprises a p-well region, an n+ region and a p+ region, wherein the n+ region and a portion of p+ region are disposed in the p-well region which is adjacent to the n+ region. The epitaxial channel is disposed over the drift layer and covers at least a portion of the n+ region. The epitaxial channel is composed of at least two epitaxial layers whose conduction types or doping concentrations are not identical. The gate oxide layer is disposed on the epitaxial channel. The gate metal is disposed on the gate oxide layer. The isolation layer is disposed on the gate metal and the gate oxide layer.Type: ApplicationFiled: September 30, 2014Publication date: October 8, 2015Applicants: ACREO SWEDISH ICT AB, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Tyng YEN, Mietek BAKOWSKI, Chien-Chung HUNG, Sergey RESHANOV, Adolf SCHONER, Chwan-Ying LEE