Patents by Inventor Cheng Wei

Cheng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848290
    Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
  • Publication number: 20230400784
    Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.
    Type: Application
    Filed: July 28, 2023
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua WANG, Chueh-Chi KUO, Kuei-Lin HO, Zong-You YANG, Cheng-Wei SUN, Wei-Yuan CHEN, Cheng-Chieh CHEN, Heng-Hsin LIU, Li-Jui CHEN
  • Publication number: 20230402508
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, a stack of nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, an air spacer disposed between the S/D region and the fin base, and a dielectric layer disposed between the air spacer and the fin base.
    Type: Application
    Filed: March 29, 2023
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Lun-Kuang TAN, Chi-Yu CHOU, Yueh-Ching PAI
  • Publication number: 20230391598
    Abstract: A prying tool includes a main body, a wheel frame and a wheel assembly. The main body is provided with a prying portion, a connecting portion, and a supporting portion curvedly formed between the prying portion and the connecting portion. The wheel frame is detachably connected to the connecting portion. The wheel assembly includes a first wheel rotatably mounted to the wheel frame. Therefore, the prying tool can carry an object by the wheel assembly after prying the object.
    Type: Application
    Filed: April 18, 2023
    Publication date: December 7, 2023
    Inventor: Cheng-Wei SU
  • Publication number: 20230387316
    Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
  • Publication number: 20230388791
    Abstract: A power saving method for lower-power devices is disclosed. Unencrypted IoT packets are received from low-power sensors. An identity of a mobile device is registered and public keys are exchanged between an MQTT agent and the mobile device. An advanced encryption standard (AES) key is generated according to public and private keys of the MQTT agent and a public key of the mobile device and received IoT packets are encrypted using the AES key. The encrypted IoT packets are transmitted to an MQTT broker. The MQTT broker forward the encrypted IoT packets to the mobile device. The mobile device exchanges the AES key with the electronic device according to its own public key through the secure shell (SSH) mechanism. The mobile device decrypts the IoT packets through the AES key.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventor: CHENG-WEI HU
  • Publication number: 20230386913
    Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Publication number: 20230381956
    Abstract: The present disclosure provides a multi-arm spacecraft model predictive control method based on the mixture of Gaussian processes, equipment, and a medium. Model predictive control has excellent performance in dealing with complex nonlinear systems such as multi-arm spacecrafts with various constraints, and is widely applied to ground robots, unmanned aerial vehicles, autonomous driving and other practical scenarios. Therefore, a task space controller is designed based on the model predictive control in the present disclosure. Besides, in order to enhance the anti-interference capability of the present disclosure, an interference model is established and compensation is carried out in the model predictive control by utilizing the characteristics of small training data volume and high training speed in the mixture of Gaussian processes. Finally, a thrust distribution method is designed to complete platform control.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 30, 2023
    Inventors: Chengfei Yue, Xibin Cao, Ziran Liu, Xueqin Chen, Fan Wu, Cheng Wei
  • Patent number: 11830648
    Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 28, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chieh-Pin Chang, Cheng-Wei Luo, Kai-Yi Huang, Ta-Hsun Yeh
  • Publication number: 20230375947
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Shao-Hua WANG, Kueilin HO, Cheng Wei SUN, Zong-You YANG, Chih-Chun CHIANG, Yi-Fam SHIU, Chueh-Chi KUO, Heng-Hsin LIU, Li-Jui CHEN
  • Publication number: 20230378316
    Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Yi-Ying LIU, Yueh-Ching PAI
  • Publication number: 20230375684
    Abstract: A target measurement device is provided. The target measurement device includes a fixing ring, a main body, and a transceiver. The fixing ring has a first surface. The main body is over the first surface of the fixing ring. The transceiver is coupled to the main body. The transceiver is at least movable between a center of the fixing ring to an edge of the fixing ring from a top view perspective. A method for measuring a target is also provided.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Inventors: PRADIP GIRDHAR CHAUDHARI, CHE-HUI LEE, CHIH-CHENG WEI, WEN-CHENG YANG, CHYI-TSONG NI
  • Patent number: 11822745
    Abstract: Provided are a driving method of a touch display panel, a driving circuit and a touch display device. The driving method includes: obtaining a touch position of an active stylus; determining a first region on the touch display panel based on the touch position of the active stylus; and transmitting an uplink (UL) signal to touch sensing electrodes in the first region and transmitting an anti-interference signal to the touch sensing electrodes in at least a part of the region except for the first region on the touch display panel during an UL transmission period, wherein the UL signal transmitted to the touch sensing electrodes in the first region during the UL transmission period is for transmission to the active stylus.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 21, 2023
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Hao-Wei Cheng, Cheng-Wei Pan
  • Publication number: 20230371405
    Abstract: A structure comprising a top electrode and a bottom electrode. The structure further comprises a multilayer stack disposed between the top electrode and the bottom electrode, where the multilayer stack comprises alternating confinement layers and phase-change material layers, and where at least two of the phase-change material layers have different doping concentrations of at least one dopant.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Inventors: Kevin W. Brew, JIN PING HAN, Timothy Mathew Philip, Cheng-Wei Cheng, ROBERT L. BRUCE, Matthew Joseph BrightSky
  • Publication number: 20230369395
    Abstract: Nanostructure transistors are formed in a manner that may reduce the likelihood of source/drain region merging in the nanostructure transistors. In a top-down view of a nanostructure transistor described herein, source/drain regions on opposing sides of a nanostructure channel of the nanostructure transistor are staggered such that the distance between the source/drain regions is increased. This reduces the likelihood of the source/drain regions merging, which reduces the likelihood of failures and/or other defects forming in the nanostructure transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate the miniaturization of semiconductor devices that include nanostructure transistors while maintaining and/or increasing the semiconductor device yield of the semiconductor devices.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 16, 2023
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Lun-Kuang TAN, Chi-Yu CHOU, Yueh-Ching PAI
  • Patent number: 11818971
    Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Ruilong Xie, Nanbo Gong, Cheng-Wei Cheng
  • Publication number: 20230363080
    Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Wei Lu, Kuang-Hua Wang
  • Patent number: 11811326
    Abstract: An example circuit includes a loop controller having current phase inputs, a feedback input, a control loop output and a transient event output. The feedback input is adapted to be coupled to an output terminal of a multi-phase power stage. A PWM circuit has a blanking input, a control input and a PWM output, the control input coupled to the control loop output. A phase management circuit has a transient detect input, a PWM input, a blanking output and phase outputs. The transient detect input is coupled to the transient event output. The PWM input is coupled to the PWM output and the blanking output is coupled to the blanking input. Each of the phase outputs is adapted to be coupled to a respective phase of the multi-phase power stage. The phase management circuit is configured to provide a blanking control signal representative of a variable blanking time.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: November 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naman Bafna, Cheng Wei Chen, Preetam Charan Anand Tadeparthy, Sreelakshmi Suresh, Ammineni Balaji
  • Patent number: 11812166
    Abstract: A display system includes a camera, a processor and a display. The camera is configured to shoot a first image and a second image in order. The processor is configured to generate a third image when a difference between the first image and the second image is larger than or equal to a preset difference value. The display is configured to display the first image and the third image in order when the difference is larger than or equal to the preset difference value. A display method and an image capture device are also disclosed herein.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: November 7, 2023
    Assignee: AVer Information Inc.
    Inventors: Cheng-Wei Huang, Han-Yen Chang
  • Patent number: D1006572
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su