Patents by Inventor Cheng Wei

Cheng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANTI-SLIP FASTENER DRIVER
    Publication number: 20240109170
    Abstract: An anti-slip fastener driver includes a shank and a driving portion formed on an end of the shank and defining a longitudinal axis. The driving portion includes an outer periphery surrounding the longitudinal axis and having a first peripheral face. An end of the driving portion opposite to the shank includes a first bevel face connected to the first peripheral face. The first bevel face includes a first side and a first corner opposite to the first side. The end of the driving portion opposite to the shank defines a reference plane perpendicular to the longitudinal axis. The first side is located on the reference plane. The first corner is located between the reference plane and the shank.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventor: Cheng-Wei SU
  • SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF
    Publication number: 20240105787
    Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.
    Type: Application
    Filed: February 1, 2023
    Publication date: March 28, 2024
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
  • ELECTRONIC DEVICE
    Publication number: 20240105739
    Abstract: An electronic device includes a substrate, a conductive structure disposed on the substrate, and a first insulating island disposed on the conductive structure. The conductive structure includes a first conductive component, a second conductive component, and a third conductive component. The third conductive component is disposed on the first conductive component and the second conductive component. The third conductive component is electrically connected to the first conductive component and the second conductive component. In a cross-sectional view of the electronic device, the width of the first insulating island is greater than the width of the third conductive component.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Wen-Bin HUNG, Cheng-Wei LEE
  • Power supply
    Patent number: 11942857
    Abstract: A power supply is provided. The power supply includes a power supply circuit and a control circuit. The power supply circuit includes a voltage converter and multiple point-of-load circuits. The voltage converter generates a third voltage according to a first voltage. The load point-of-load circuits generate at least one second voltage and at least one state signal according to the third voltage. The at least one second voltage is suitable for supplying power to a load. The control circuit is coupled to the power supply circuit. The control circuit determines whether a single event latch-up occurs in the power supply circuit according to the at least one state signal. When the single event latch-up occurs in the power supply circuit, the control circuit switches off the power supply circuit to stop generating the at least one second voltage and the at least one state signal.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Wei Yang, Chueh-Hao Yu, Chien-Yu Chen
  • HYBRID CONDUCTIVE STRUCTURES
    Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Pharmaceutical compositions containing mixed polymeric micelles
    Patent number: 11931456
    Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 19, 2024
    Assignee: MegaPro Biomedical Co. Ltd.
    Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang
  • Method of making slow wave inductive structure
    Patent number: 11929196
    Abstract: A method of making a slow wave inductive structure includes depositing a first dielectric layer over a first substrate. The method further includes forming a first conductive winding in the first dielectric layer. The method further includes bonding a second substrate to the first dielectric layer, wherein the second substrate is physically separated from the first conductive winding, and the second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm. The method further includes depositing a second dielectric layer over the second substrate. The method further includes forming a second conductive winding in the second dielectric layer, wherein the second substrate is physically separated from the second conductive winding.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Display panel
    Patent number: 11930663
    Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 12, 2024
    Assignee: Au Optronics Corporation
    Inventors: Bo-Chen Chen, Yun-Ru Cheng, Ya-Ling Hsu, Chia-Hsuan Pai, Cheng-Wei Huang, Wei-Shan Chao
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20240072055
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate comprising an NMOS region and a PMOS region abutting the NMOS region, a first shallow trench isolation (STI) disposed across the PMOS region and the NMOS region, the first STI has a first bottom being slanted from the NMOS region towards the PMOS region. The semiconductor device structure also includes a first fin disposed in the PMOS region, a first source/drain epitaxial feature disposed over the first fin, a second fin disposed in the NMOS region, a second source/drain epitaxial feature disposed over the second fin, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, the first dielectric feature having a portion embedded in the first STI.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Shahaji B. MORE, Cheng-Wei Chang
  • Highly symmetric integrated inductor
    Patent number: 11916098
    Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 27, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
  • Direct growth of lateral III-V bipolar transistor on silicon substrate
    Patent number: 11916130
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 27, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Current Sharing Apparatus and Control Method
    Publication number: 20240063627
    Abstract: An apparatus includes a plurality of switches connected in parallel between an input terminal and an output terminal of a power bus, a plurality of current sensing circuits coupled to the plurality of switches, wherein each current sensing circuit is coupled to a corresponding switch, and a plurality of current sharing circuits configured to receive current sensing signals from the plurality of current sensing circuits and generate a plurality of gate drive signals to control the plurality of switches so as to achieve a predetermined current distribution among the plurality of switches.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Wenkai Wu, Yingqian Ma, Cheng-Wei Chen, Weidong Zhu, Qian Chen
  • Isolation Structures in Semiconductor Devices
    Publication number: 20240055476
    Abstract: A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.
    Type: Application
    Filed: April 10, 2023
    Publication date: February 15, 2024
    Inventors: Cheng-Wei Chang, Shahaji B. More, Lun-Kuang Tan, Chi-Yu Chou, Yueh-Ching Pai
  • Opener
    Patent number: D1015835
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Wrench
    Patent number: D1015837
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Opener
    Patent number: D1016583
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Head portion of a ratchet wrench
    Patent number: D1016584
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Driving tool
    Patent number: D1016588
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 5, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Head portion of a ratchet wrench
    Patent number: D1017355
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 12, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su
  • Adapter
    Patent number: D1017357
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Hong Ann Tool Industries Co., Ltd.
    Inventor: Cheng-Wei Su