Patents by Inventor Cheng-Wen Fan
Cheng-Wen Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8637936Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.Type: GrantFiled: September 25, 2009Date of Patent: January 28, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
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Patent number: 8350337Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.Type: GrantFiled: December 29, 2009Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Patent number: 8349682Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: GrantFiled: May 2, 2012Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8252657Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: GrantFiled: March 27, 2011Date of Patent: August 28, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20120214284Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: ApplicationFiled: May 2, 2012Publication date: August 23, 2012Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8193900Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: GrantFiled: June 24, 2009Date of Patent: June 5, 2012Assignee: United Microelectronics Corp.Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8133792Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.Type: GrantFiled: July 4, 2006Date of Patent: March 13, 2012Assignee: United Microelectronics Corp.Inventors: Victor-Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
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Patent number: 8114752Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.Type: GrantFiled: February 6, 2010Date of Patent: February 14, 2012Assignee: United Microelectronics Corp.Inventors: Victor Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
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Patent number: 8093118Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.Type: GrantFiled: June 26, 2009Date of Patent: January 10, 2012Assignee: United Microelectronics Corp.Inventors: Kun-Szu Tseng, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Patent number: 7994576Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: GrantFiled: June 22, 2009Date of Patent: August 9, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20110171810Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: ApplicationFiled: March 27, 2011Publication date: July 14, 2011Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20110156161Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Publication number: 20110073957Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
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Publication number: 20100328022Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Publication number: 20100327378Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Applicant: United Microelectronics Corp.Inventors: KUN-SZU TSENG, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Publication number: 20100320544Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20100140741Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.Type: ApplicationFiled: February 6, 2010Publication date: June 10, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Victor Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
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Publication number: 20080029854Abstract: The invention is directed to a conductive shielding pattern for shielding a inductor device. The conductive shielding pattern comprises a plurality of conductive layers and a plurality of diffusion regions. The conductive layers are located on a substrate. The diffusion regions are located in the substrate and the conductive layers and the diffusion regions are arranged alternatively and are free ends respectively.Type: ApplicationFiled: August 3, 2006Publication date: February 7, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Chou Hung, Hua-Chou Tseng, Yu-Chia Chen, Victor-Chiang Liang, Cheng-Wen Fan
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Publication number: 20080012092Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.Type: ApplicationFiled: July 4, 2006Publication date: January 17, 2008Inventors: Victor-Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
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Patent number: 7271428Abstract: The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the emitter and on the first extrinsic base region. The first extrinsic base region is adjacent the intrinsic base region and the second extrinsic base region is adjacent the first extrinsic base region on the substrate, wherein a dopant concentration of the second extrinsic base region is higher than a dopant concentration of the first extrinsic base region.Type: GrantFiled: December 21, 2004Date of Patent: September 18, 2007Assignee: United Microelectronics Corp.Inventors: Cheng-Wen Fan, Hua-Chou Tseng