Patents by Inventor Cheng-Wen Wu

Cheng-Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210401867
    Abstract: The present disclosure provides a heavy atom carrier and a method of treating cancer using the heavy atom carriers in conjunction with monochromatic X-ray. The heavy atom carriers are halogen-containing heavy atom carriers.
    Type: Application
    Filed: April 1, 2019
    Publication date: December 30, 2021
    Inventors: CHENG-WEN WU, ERH-HSUAN LIN, WAN-TING TSENG
  • Publication number: 20200268839
    Abstract: The present disclosure provides a nucleic acid fragment, a pharmaceutical composition, and a therapeutic process for treating a subject having chronic obstructive pulmonary disease (COPD). Especially, the nucleic acid fragment, the pharmaceutical composition, and the therapeutic process are therapeutic-efficient for treating pulmonary fibrosis and emphysema of the subject, as demonstrated in this disclosure.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 27, 2020
    Inventors: Cheng-Wen WU, Erh-Hsuan LIN, Ching-Huei LIN
  • Publication number: 20200062738
    Abstract: A compound for inhibiting BMI-1/MCL-1 having a structure of Formula (I), wherein the various groups are as described. A pharmaceutical composition for treating cancer includes an effective amount of a compound of Formula (I).
    Type: Application
    Filed: April 30, 2018
    Publication date: February 27, 2020
    Applicants: Development Center for Biotechnology, National Yang-Ming University
    Inventors: Cheng-Wen Wu, Erh-Hsuan Jiann Lin, Chi-Ying Huang, Jia-Ming Chang, Shih-Hsien Chuang, Hui-Jan Hsu, Wei-Wei Chen
  • Patent number: 9905277
    Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 27, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Wen Luo, Hsiu-Chuan Shih, Chi-Kang Chen, Ding-Ming Kwai, Cheng-Wen Wu
  • Publication number: 20170003908
    Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.
    Type: Application
    Filed: October 21, 2015
    Publication date: January 5, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Wen LUO, Hsiu-Chuan SHIH, Chi-Kang CHEN, Ding-Ming KWAI, Cheng-Wen WU
  • Patent number: 8977942
    Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 10, 2015
    Assignee: National Tsing Hua University
    Inventors: Shu-Yu Wu, Cheng-Wen Wu
  • Patent number: 8937486
    Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 20, 2015
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung-Fa Chou
  • Publication number: 20140157076
    Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: SHU-YU WU, CHENG-WEN WU
  • Patent number: 8742839
    Abstract: This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 3, 2014
    Assignee: National Tsing Hua University
    Inventors: Hsiu-Chuan Shih, Cheng-Wen Wu
  • Publication number: 20140062586
    Abstract: This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current.
    Type: Application
    Filed: December 14, 2012
    Publication date: March 6, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: HSIU-CHUAN SHIH, CHENG-WEN WU
  • Publication number: 20140004072
    Abstract: A method and a composition of gene therapy for treating acute lung injury (ALI) and acute respiratory distress syndrome (ARDS) based on polyplexes formed between linear polyethyleneimine (PEI) and DNA comprising the ?2-Adrenergic Receptor (?2AR) gene are provided.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: NATIONAL YANG MING UNIVERSITY
    Inventors: Cheng-Wen Wu, Erh-Hsuan Lin, Hsiang-Yi Chang
  • Publication number: 20130293255
    Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.
    Type: Application
    Filed: July 11, 2013
    Publication date: November 7, 2013
    Inventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung- Fa Chou
  • Patent number: 8531199
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 10, 2013
    Assignee: National Tsing Hua University
    Inventors: Cheng Wen Wu, Po Yuan Chen, Ding Ming Kwai, Yung Fa Chou
  • Patent number: 8443032
    Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 14, 2013
    Assignee: National Tsing Hua University
    Inventors: Chen Hsing Wang, Chieh Lin Chuang, Cheng Wen Wu
  • Patent number: 8307261
    Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 6, 2012
    Assignee: National Tsing Hua University
    Inventors: Cheng Wen Wu, Te Hsuan Chen, Yu Ying Hsiao, Yu Tsao Hsing
  • Publication number: 20120133807
    Abstract: An image capture apparatus comprises an image sensor array including a plurality of image sensors arranged in a two-dimensional (2-D) array and an analog-to-digital converter (ADC) array including a plurality of ADCs arranged in a 2-D array. The image sensor array is divided into a plurality of sub-arrays, each of which includes at least two image sensors. The image sensor array is vertically stacked on the ADC array. Each ADC corresponds to one sub-array of image sensors and is coupled to process signals output by the image sensors in the corresponding sub-array.
    Type: Application
    Filed: December 23, 2010
    Publication date: May 31, 2012
    Inventors: Cheng-Wen Wu, Ding-Ming Kwai, Jim Li, Ka-Yi Yeh
  • Patent number: 8160413
    Abstract: A fiber loop formed by bending of a connection section between the first fiber and the second fiber includes a coupling region and an upper taper region as well as a down taper region arranged symmetrically on two sides of the coupling region. Then the fiber optic splitter with the fiber loop is assembled with a splitting ratio modulation mechanism. Thus the manufacturing of the fiber optic power splitter with variable splitting ratio is simplified and this favors production and applications of the device. Moreover, the splitting and modulation quality of the splitter are stable and are controlled precisely. Thus the economic benefits of the device in manufacturing, operation quality and product competitiveness are all improved.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: April 17, 2012
    Assignee: Feng Chia University
    Inventor: Cheng-Wen Wu
  • Patent number: 8095832
    Abstract: A method for repairing a main memory comprises the steps of: utilizing a spare memory to repair a main memory, wherein the spare memory includes a plurality of spare memory units; allocating a spare memory unit; determining whether available permutations of the allocated spare memory unit cover a newly found defect in the main memory; removing permutations of the spare memory unit failing to cover newly found defects in the main memory; and allocating another spare memory unit to repair the newly found defects if available permutations of the allocated spare memory unit fails to cover the newly found defects.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: January 10, 2012
    Assignee: National Tsing Hua University
    Inventors: Mincent Lee, Cheng Wen Wu
  • Publication number: 20110080185
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Application
    Filed: May 6, 2010
    Publication date: April 7, 2011
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHENG WEN WU, PO YUAN CHEN, DING MING KWAI, YUNG FA CHOU
  • Publication number: 20110080184
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHENG WEN WU, PO YUAN CHEN, DING MING KWAI, YUNG FA CHOU