Patents by Inventor Cheng-Wen Wu
Cheng-Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152679Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
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Patent number: 11942420Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: GrantFiled: June 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11914941Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.Type: GrantFiled: April 19, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
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Patent number: 11915512Abstract: A three-dimensional sensing system includes a plurality of scanners each emitting a light signal to a scene to be sensed and receiving a reflected light signal, according to which depth information is obtained. Only one scanner executes transmitting corresponding light signal and receiving corresponding reflected light signal at a time.Type: GrantFiled: October 14, 2021Date of Patent: February 27, 2024Assignee: Himax Technologies LimitedInventors: Ching-Wen Wang, Cheng-Che Tsai, Ting-Sheng Hsu, Min-Chian Wu
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Publication number: 20210401867Abstract: The present disclosure provides a heavy atom carrier and a method of treating cancer using the heavy atom carriers in conjunction with monochromatic X-ray. The heavy atom carriers are halogen-containing heavy atom carriers.Type: ApplicationFiled: April 1, 2019Publication date: December 30, 2021Inventors: CHENG-WEN WU, ERH-HSUAN LIN, WAN-TING TSENG
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Publication number: 20200268839Abstract: The present disclosure provides a nucleic acid fragment, a pharmaceutical composition, and a therapeutic process for treating a subject having chronic obstructive pulmonary disease (COPD). Especially, the nucleic acid fragment, the pharmaceutical composition, and the therapeutic process are therapeutic-efficient for treating pulmonary fibrosis and emphysema of the subject, as demonstrated in this disclosure.Type: ApplicationFiled: February 24, 2020Publication date: August 27, 2020Inventors: Cheng-Wen WU, Erh-Hsuan LIN, Ching-Huei LIN
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Publication number: 20200062738Abstract: A compound for inhibiting BMI-1/MCL-1 having a structure of Formula (I), wherein the various groups are as described. A pharmaceutical composition for treating cancer includes an effective amount of a compound of Formula (I).Type: ApplicationFiled: April 30, 2018Publication date: February 27, 2020Applicants: Development Center for Biotechnology, National Yang-Ming UniversityInventors: Cheng-Wen Wu, Erh-Hsuan Jiann Lin, Chi-Ying Huang, Jia-Ming Chang, Shih-Hsien Chuang, Hui-Jan Hsu, Wei-Wei Chen
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Patent number: 9905277Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.Type: GrantFiled: October 21, 2015Date of Patent: February 27, 2018Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Pei-Wen Luo, Hsiu-Chuan Shih, Chi-Kang Chen, Ding-Ming Kwai, Cheng-Wen Wu
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Publication number: 20170003908Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.Type: ApplicationFiled: October 21, 2015Publication date: January 5, 2017Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Pei-Wen LUO, Hsiu-Chuan SHIH, Chi-Kang CHEN, Ding-Ming KWAI, Cheng-Wen WU
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Patent number: 8977942Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.Type: GrantFiled: March 15, 2013Date of Patent: March 10, 2015Assignee: National Tsing Hua UniversityInventors: Shu-Yu Wu, Cheng-Wen Wu
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Patent number: 8937486Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.Type: GrantFiled: July 11, 2013Date of Patent: January 20, 2015Assignee: National Tsing Hua UniversityInventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung-Fa Chou
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Publication number: 20140157076Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.Type: ApplicationFiled: March 15, 2013Publication date: June 5, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: SHU-YU WU, CHENG-WEN WU
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Patent number: 8742839Abstract: This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current.Type: GrantFiled: December 14, 2012Date of Patent: June 3, 2014Assignee: National Tsing Hua UniversityInventors: Hsiu-Chuan Shih, Cheng-Wen Wu
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Publication number: 20140062586Abstract: This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current.Type: ApplicationFiled: December 14, 2012Publication date: March 6, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: HSIU-CHUAN SHIH, CHENG-WEN WU
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Publication number: 20140004072Abstract: A method and a composition of gene therapy for treating acute lung injury (ALI) and acute respiratory distress syndrome (ARDS) based on polyplexes formed between linear polyethyleneimine (PEI) and DNA comprising the ?2-Adrenergic Receptor (?2AR) gene are provided.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: NATIONAL YANG MING UNIVERSITYInventors: Cheng-Wen Wu, Erh-Hsuan Lin, Hsiang-Yi Chang
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Publication number: 20130293255Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.Type: ApplicationFiled: July 11, 2013Publication date: November 7, 2013Inventors: Cheng-Wen Wu, Po-Yuan Chen, Ding-Ming Kwai, Yung- Fa Chou
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Patent number: 8531199Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.Type: GrantFiled: May 6, 2010Date of Patent: September 10, 2013Assignee: National Tsing Hua UniversityInventors: Cheng Wen Wu, Po Yuan Chen, Ding Ming Kwai, Yung Fa Chou
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Patent number: 8443032Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.Type: GrantFiled: March 27, 2008Date of Patent: May 14, 2013Assignee: National Tsing Hua UniversityInventors: Chen Hsing Wang, Chieh Lin Chuang, Cheng Wen Wu
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Patent number: 8307261Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.Type: GrantFiled: May 4, 2009Date of Patent: November 6, 2012Assignee: National Tsing Hua UniversityInventors: Cheng Wen Wu, Te Hsuan Chen, Yu Ying Hsiao, Yu Tsao Hsing