Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.

Abstract: The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract: The present invention discloses a method for rapid assessment of lung cancer therapy efficacy in a few days instead of weeks by conventional imaging methods. This method can also be used to detect relapse of the cancer and to improve the current TNM cancer staging method for more accurate prognosis. The rapid assessment of therapy efficacy is based on detecting circulating cancer cells in body fluid with high positive detection rate. The high positive detection rate is achieved by using PCR amplification of multiple marker genes identified by in silico search of DNA sequence database. This invention also discloses a scoring method to calculate the cancer cell load based on PCR results to correlate the amount of circulating cancer cells in lung cancer patients with their treatment outcomes.

Abstract: The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

Abstract: A semiconductor memory employs the redundancy memory technique and the error correction code technique and method of correcting errors. The method of correcting errors reads data bits and a checking bit from a predetermined unit of a first memory array such as a main memory array, and the data bits are checked based on the checking bit to determine if there is any error. If there is an error in the data bits, the checking bit is used to correct the error and the data bits together with the checking bit are written back to the predetermined unit. If there is still error in the data bits after the read-check-write process is repeated a predetermined number of times, the predetermined unit is marked as a faulty unit and the data bits together with the checking bit are written to a second memory array such as a redundancy memory array.

Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Abstract: An apparatus for multiple polynomial-based random number generation includes an LUT device having a plurality of polynomials established therein, a signal selection unit coupled to the LUT device and operable so as to generate a select signal that is inputted to the LUT device to thereby select at least one of the polynomials established in the LUT device, and an LFSR device coupled to the LUT device and operable so as to perform LFSR operations based on the at least one of the polynomials selected from the LUT device. A method for multiple polynomial-based random number generation includes: a) establishing the polynomials in the LUT device, b) generating the select signal to select at least one of the polynomials, and c) enabling the LFSR device to perform the corresponding LFSR operations.

Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure.

Abstract: A method and system of fault patterns oriented defect diagnosis for memories can analyze and recognize fault patterns and failure patterns after Memory Error Catches and Analyses (MECA) are done. The existent fault patterns are compared with a pre-simulated and grouped defect dictionary that defines possible defects of different fault patterns, and the defects of memories caused from their manufacturing process or circuit layout can be detected.

Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Abstract: A method of determining whether a subject is suffering from or at risk for developing cancer. The method includes preparing a nucleic acid sample from a subject, and identifying a single nucleotide polymorphism in the SERPINB13 gene. The presence of a single nucleotide polymorphism indicates that the subject is suffering from or at risk for developing cancer. Also disclosed is a method of treating cancer by administering to a subject in need thereof an effective amount of a nucleic acid encoding the Hurpin protein or an effective amount of the Hurpin protein.

Abstract: This invention is based on the discovery of an association of Collapsin Response Mediator Protein-1 (CRMP-1) with tumor metastasis. The level of CRMP-1 protein or mRNA can be used as an indicator of cellular invasiveness and of a test compound's ability to alter cellular invasiveness. The level of CRMP-1 protein can also be altered, e.g., to reduce invasiveness.

Abstract: Many genes are identified as being metastasis associated. Identifying and profiling of these genes expression can be used to evaluate a sample, to diagnose tumor invasive potential or metastatic development in a sample, or screen for a test compound useful in the prevention or treatment of tumor metastasis.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.