Abstract: A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.

Abstract: In a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure and an encapsulant surrounds the two or more semiconductor dies. An integrated passive device (IPD) is connected on a second side of the redistribution structure. The second side is opposite to the first side and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. Two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure.

Abstract: A method includes forming a metal pad, depositing a passivation layer on the metal pad, and planarizing the passivation layer, so that the passivation layer includes a planar top surface. The method further includes etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening, and forming a conductive via including a lower portion in the opening, and an upper portion higher than the passivation layer. A polymer layer is then dispensed to cover the conductive via.

Abstract: In an embodiment, a device includes: an interposer including: a back-side redistribution structure; an interconnection die over the back-side redistribution structure, the interconnection die including a substrate, a through-substrate via protruding from the substrate, and an isolation layer around the through-substrate via; a first encapsulant around the interconnection die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through-substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via that physically contacts the through-substrate via, the isolation layer separating the first conductive via from the substrate.

Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Abstract: A key structure includes a light source and a light guiding assembly, a transparent cover, a semi-transparent and semi-reflective mirror, and a reflection mirror disposed above the light source. The light guiding assembly includes a center column and a platform surrounding the center column. A bottom surface of the center column faces the light source. The transparent cover is disposed on the light guiding assembly and covers the center column and the platform. An exterior side wall of the transparent cover has strip recesses surrounding the center column and the platform. The reflection mirror is disposed in the light guiding assembly. The reflection mirror and the semi-transparent and semi-reflective mirror face each other through the transparent cover. A part of light generated by the light source generates an infinity reflection between the strip recesses, the reflection mirror, and the semi-transparent and semi-reflective mirror after passing through the light guiding assembly.

Abstract: A key structure includes a light source and a light guiding assembly, a transparent cover, a semi-transparent and semi-reflective mirror, and a reflection mirror disposed above the light source. The light guiding assembly includes a center column and a platform surrounding the center column. A bottom surface of the center column faces the light source. The transparent cover is disposed on the light guiding assembly and covers the center column and the platform. An exterior side wall of the transparent cover has strip recesses surrounding the center column and the platform. The reflection mirror is disposed in the light guiding assembly. The reflection mirror and the semi-transparent and semi-reflective mirror face each other through the transparent cover. A part of light generated by the light source generates an infinity reflection between the strip recesses, the reflection mirror, and the semi-transparent and semi-reflective mirror after passing through the light guiding assembly.

Abstract: A competition evaluation system and an evaluation method that provide a user unit for a plurality of players to respectively create a competition member list. The competition member list is generated by selecting at least one of a plurality of competition members by the player. The competition members respectively have a competition result and an appearance information, and each of the competition members is respectively given a performance score and a contribution degree based on the competition result and the appearance information. The invention uses a statistics unit to positively correlatedly correct the performance score of the competition member based on the contribution degree of each of the competition members to generate a weighted score for the competition member, thereby generating a total score for each of the competition member lists, and performing ranking according to the total score, so that the associated players respectively obtain a competition ranking.

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: An electronic device includes a first buffer, a second buffer, and a multiplexer. The first buffer receives and stores first data when the first buffer is not full, and performs a First-In-First-Out (FIFO) operation on the first data. The second buffer receives and stores second data when the first buffer is full, and performs the FIFO operation on the second data. The multiplexer is electrically connected between the first buffer and the second buffer. The multiplexer receives the first data from outside of the electronic device, or it receives the second data from the second buffer. A depth of the first buffer is less than that of the second buffer.

Abstract: A pivoting mechanism for a spring hinge includes a pin and at least one cap assembly. The pin defines an axial direction and is configured to be disposed through a barrel portion of the spring hinge. The at least one cap assembly is disposed on an end of the pin and includes a cap body, a restricting member and an engaging member. The cap body includes a first abutting wall lateral to the axial direction, a first circumferential wall extending around the axial direction and connected with the first abutting wall and a groove recessed on an inner surface of the first circumferential wall. The restricting member is embedded within the groove and radially protrudes beyond the inner surface. The engaging member surrounds the pin and is disposed between the restricting member and the first abutting wall.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate and a plurality of memory devices disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. A dummy gate structure is arranged on the first isolation structure and has a top surface that is vertically above top surfaces of the plurality of transistor devices and the plurality of memory devices.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: This application discloses a nanoscale failure analysis method, including step 1: placing a first sample to be analyzed on a sample stage of an FIB machine, and performing cutting on a selected area of the first sample by using an ion beam in the FIB machine to form a first cross section and expose a metal pattern on the first cross section; step 2: depositing a protective layer on the first cross section by using an electron beam of the FIB machine; step 3: transferring the first sample to a nano prober, the protective layer being used for protecting the metal pattern and preventing metal diffusion in a transfer process; step 4: performing surface micro treatment on the first sample by using an ion source in the nano prober to remove the protective layer; step 5: performing probing on the metal pattern and implementing electrical testing through the nano prober.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: Mechanisms are provided for intrusion detection based on regular expression matching. The mechanisms partition a regular expression (RegEx) rule set into a plurality of different partitions and distributes the plurality of different partitions to a plurality of different edge computing devices associated with a protected network of computing resources. The mechanisms route data packets of an incoming data stream to the plurality of edge computing devices, each of which processes the data packets to determine whether the data packets match RegEx rules in a partition distributed to the edge computing device. A determination is made as to whether the incoming data stream represents an intrusion based on a combination of results of the processing of the data packets by the plurality of edge computing devices.