Patents by Inventor Cheng Yan

Cheng Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250054750
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a first semiconductor layer on an inner surface of a trench of a substrate; forming a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate; forming another first semiconductor layer on the second semiconductor layer on the inner surface of the trench of the substrate; forming another second semiconductor layer on the another first semiconductor layer on the inner surface of the trench of the substrate, in which the second semiconductor layer is sandwiched between the first semiconductor layer and the another first semiconductor layer, and the another first semiconductor layer is sandwiched between the second semiconductor layer and the another second semiconductor layer; and forming a third semiconductor layer on the another second semiconductor layer.
    Type: Application
    Filed: October 27, 2024
    Publication date: February 13, 2025
    Inventors: Kai Hung LIN, Cheng Yan JI
  • Patent number: 12224328
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a word line structure. The semiconductor substrate has an active region. The word line structure is disposed in the active region of the semiconductor substrate. The word line structure includes a first work function layer, a second work function layer, and a buffer structure. The second work function layer is on the first work function layer. The buffer structure is between the first work function layer and the second work function layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 11, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Yan Ji, Wei-Tong Chen
  • Publication number: 20240421273
    Abstract: A light-emitting device and a manufacturing method thereof are provided. The light-emitting device includes a light-emitting chip, a first reflective layer, a light-permeable layer, an adhesive material, and a second reflective layer. The light-emitting chip has a light-emitting surface. The first reflective layer surrounds a first side surface of the light-emitting chip. The light-permeable layer is disposed on the light-emitting surface of the light-emitting chip and has a light-exiting surface and a second side surface. The adhesive material has a central portion and an extension portion. The central portion corresponds to the light-emitting surface. The extension portion is connected to the central portion and is located on a first upper surface of the first reflective layer. The second reflective layer is disposed on the first reflective layer to surround the second side surface of the light-permeable layer and cover the extension portion.
    Type: Application
    Filed: April 11, 2024
    Publication date: December 19, 2024
    Inventors: CHENG-YAN HSIEH, Jie-Ting Tsai, KUO-MING CHIU
  • Patent number: 12159786
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: depositing a first semiconductor layer on an inner surface of a trench of a substrate; depositing a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate, in which a dopant concentration of the first semiconductor layer is less than a dopant concentration of the second semiconductor layer; and depositing a third semiconductor layer on the second semiconductor layer to fill the trench of the substrate, in which a dopant concentration of the third semiconductor layer is less than the dopant concentration of the second semiconductor layer.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: December 3, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Kai Hung Lin, Cheng Yan Ji
  • Publication number: 20240387260
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure including the following steps. A trench is formed between bit lines. A seed layer is deposited in the trench, and a first contact layer is deposited on the seed layer in the trench. A second contact layer is deposited on the first contact layer to fill the trench, in which a second doping concentration of the second contact layer is lower than a first doping concentration of the first contact layer. An annealing process is performed on the first contact layer and the second contact layer, such that dopants in the first contact layer diffuse into the second contact layer to form a contact plug including the first contact layer and the second contact layer.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventor: Cheng Yan JI
  • Publication number: 20240281209
    Abstract: A machine learning optimization circuit and a method thereof are provided. The method includes steps of: generating a local feature matrix from an extraction range in a feature tensor matrix, and the local feature matrix includes feature values of X columns, Y rows, and Z channels; partitioning W sub-feature matrices from the local feature matrix, and each of the W sub-feature matrices includes X×Y×Z/W feature values; simultaneously performing parallel dot product operations on the W sub-feature matrices by W×K parallel operation modules to generate W×K temporary feature matrices; and integrating the W×K temporary feature matrices into a local feature output matrix corresponding to the local feature matrix, and the local feature output matrix includes feature values of X columns, Y rows, and Z channels.
    Type: Application
    Filed: July 25, 2023
    Publication date: August 22, 2024
    Inventors: Chieh-Fu TSAI, Chia-Hsiang YANG, Cheng-Yan DU
  • Publication number: 20240161660
    Abstract: A display device and a housing of the display device are provided. The housing of the display device includes a reflective cover. The reflective cover has a plurality of segments formed on a front side of the reflective cover and a plurality of segment structures correspondingly formed on a rear side of the reflective cover. At least one of the segment structures has a notch formed thereat. Positions of the notches of the at least two adjacent ones of the segment structures are not opposite to each other.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: CHENG-YAN HSIEH, SHIH-YUAN KUO, Jie-Ting Tsai
  • Patent number: 11969236
    Abstract: A wearable device for measuring blood pressure comprises a housing with through-holes formed thereon, a processing unit disposed in the housing, a display connected to the processing unit, a plurality of sensors connected to the processing unit, the sensors being configured to transmit at least one physiological signal to the processing unit via the through-holes, and a time delay structure connected between one of the through-holes and one of the sensors and configured to lengthen a path distance between the skin surface and the sensor, wherein the processing unit is configured to determine a systolic arterial pressure and a diastolic arterial pressure by the at least one physiological signal and a Moens-Korteweg (MK) function, and to control the display to display the systolic arterial pressure and the diastolic arterial pressure to be read by the user.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 30, 2024
    Assignee: Accurate Meditech Inc
    Inventors: Kuan Jen Wang, Cheng Yan Guo, Ching-Hung Huang
  • Patent number: 11948991
    Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Publication number: 20240065664
    Abstract: A physiological signal measurement device is disclosed. In some implementations, the physiological signal measurement device includes a fixing element, a rack, a first sensor, and a second sensor. The fixing element is configured to be fixed on a limb of a user. The rack is configured to engage the fixing element and includes a first end and a second end distal to the first end. The first sensor is disposed on the first end of the rack. The sensor is disposed on the second end of the rack. The first end of the rack has a first stiffness, the second end of the rack has a second stiffness, and the first stiffness is higher than the second stiffness.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: CHENG YAN GUO, KUAN JEN WANG, PEI-MING CHIEN, HAO-CHING CHANG
  • Patent number: 11903180
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Yan Ji, Wei-Tong Chen
  • Publication number: 20240020243
    Abstract: In an example in accordance with the present disclosure, a method is described. According to the method, boundary values for a setting for a signal between a compute device and a peripheral device are determined. A target value for the setting is determined. The target value is a value between determined boundary values. The setting for the signal is adjusted to match the target value.
    Type: Application
    Filed: April 29, 2020
    Publication date: January 18, 2024
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Cheng-Yan Chiang, James L. Mondshine, Charles Shaver, Khoa Huynh, Jia-Hung Lai, Bing-Hao Cheng, Kuang-Che Teng, Chin-Yu Wang
  • Publication number: 20230413533
    Abstract: The present application provides a method of fabricating a semiconductor device. The method includes steps of forming a transistor in a substrate; depositing an insulative layer on the substrate; forming a first trench penetrating through the insulative layer to expose a portion of a first impurity region of the transistor; performing a first cyclic process comprising a first sequence of a first deposition step and a first removal step to deposit a conductive material in the first trench until a height of the conductive material in the first trench exceeds a predetermined height; filling the first trench with the conductive material after the first cyclic process; forming a storage capacitor contacting the first conductive feature; and depositing an isolation layer to cover the insulative layer and the storage capacitor.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 21, 2023
    Inventors: CHENG-YAN JI, CHU-HSIANG HSU, JING HSU
  • Publication number: 20230409767
    Abstract: Disclosed is design optimization method of the structure considering centrifugal loads and stress constraints. Compared with the prior art, this application improves the method for obtaining the relaxation coefficient c, including the calculation of the second predicted maximum stress based on the predicted stress method from steps S9.1 to S9.8. The influence of the existence of jagged boundaries and gray densities on the calculation of the structural stress field is reduced. The most important thing is to decide whether to use linear penalty or nonlinear penalty for the elastic modulus of each element according to the ratio of the number of elements with design variables less than 0.1 and greater than 0.9 to the total number of elements. Introducing the predicted maximum stress can make full use of the allowable stress of materials, improve the quality of optimization design, and obtain a design scheme with a lighter mass.
    Type: Application
    Filed: February 14, 2023
    Publication date: December 21, 2023
    Applicant: XIAMEN UNIVERSITY
    Inventors: Cheng YAN, Ce LIU, He LIU, Yuxin LIN, Cunfu WANG, Zeyong YIN
  • Publication number: 20230402313
    Abstract: The present application provides a method of fabricating a conductive feature. The method of fabricating the conductive feature includes steps of depositing an insulative layer on a substrate, forming a trench in the insulative layer, performing a cyclic process comprising a sequence of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step has been performed is equal to a first preset number of times and a number of the times the removal step has been performed is equal to a second preset number of times, and filling the trench with the conductive material after the cyclic process.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: CHENG-YAN JI, CHU-HSIANG HSU, JING HSU
  • Patent number: 11830762
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Publication number: 20230351153
    Abstract: The present invention relates to knowledge graph reasoning model, system and reasoning method based on Bayesian few-shot learning, wherein the method at least comprises: building a Gaussian mixture model to entities and relations in a knowledge graph so as to reduce uncertainty of the knowledge graph; taking each said entity as a task to simulate a meta-training process of a newly appearing entity in the dynamic knowledge graph and perform task sampling; constructing a meta learner based on a graph neural network and conducing random reasoning; and training the meta learner so as to use a support set to represent the newly appearing entity. The trained knowledge graph reasoning model in the present invention is highly adaptive and able to infer new facts or new entities without retraining.
    Type: Application
    Filed: October 5, 2022
    Publication date: November 2, 2023
    Inventors: Feng ZHAO, Cheng Yan, Hai Jin
  • Patent number: 11800985
    Abstract: The present invention provides an electrocardiographic monitoring device comprising a device body configured to be attached to a user's chest; a plurality of electrodes provided on the device body; and a controller provided on the device body and connected to the electrodes in order to obtain the user's electrocardiographic signal waveforms. The electrocardiographic monitoring device of the invention can be applied in a blood pressure monitoring system for monitoring a user's blood pressure.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 31, 2023
    Assignees: BIV MEDICAL, LTD.
    Inventors: Shiming Lin, Shih-Wei Chiang, Cheng-Yan Guo, Tai-Cun Lin, Wei-Chih Huang, Chun-Nan Chen, Ya-Ting Chang
  • Publication number: 20230335395
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: depositing a first semiconductor layer on an inner surface of a trench of a substrate; depositing a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate, in which a dopant concentration of the first semiconductor layer is less than a dopant concentration of the second semiconductor layer; and depositing a third semiconductor layer on the second semiconductor layer to fill the trench of the substrate, in which a dopant concentration of the third semiconductor layer is less than the dopant concentration of the second semiconductor layer.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Kai Hung LIN, Cheng Yan JI
  • Patent number: D1056321
    Type: Grant
    Filed: September 11, 2024
    Date of Patent: December 31, 2024
    Assignee: KLARUS LIGHTING TECHNOLOGY (HONG KONG) CO., LIMITED
    Inventors: Xiaohua Jia, Cheng Yan