Patents by Inventor Cheng-Yi Chen

Cheng-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11611973
    Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 21, 2023
    Inventors: Chiao-Chih Chang, Chien-Liang Lin, Jen-Hao Hsueh, Cheng-Che Chen, Sheng-Yi Ho, I-Wei Tsai, Zhen Jiang, Wen-Jean Yang
  • Publication number: 20230076967
    Abstract: An automatic optimization method and an automatic optimization system of a diagnosis model are provided. The automatic optimization method includes: obtaining equipment parameters; selecting a target model; selecting and converting a hyperparameter into a gene sequence, randomly generating a plurality of gene sequences to be optimized and adding them to a gene sequence set; performing a gene evolution process to generate a plurality of progeny gene sequences; performing a region search process on the plurality of progeny gene sequences to generate a plurality of new progeny gene sequences and add them to the gene sequence set; and in response to meeting the evolution completion condition, using the gene sequence set as an optimal gene sequence set for configuration of the target model and generation of a plurality of candidate diagnosis models.
    Type: Application
    Filed: October 21, 2021
    Publication date: March 9, 2023
    Inventors: CI-YI LAI, CHENG-HUI CHEN, HSAIO-YU WANG, HUAI-CHE HONG
  • Patent number: 11599190
    Abstract: In an example, an electronic device may include a housing and a first acoustic device pivotally disposed in the housing. The first acoustic device may move between a first position within the housing and a second position outside the housing. The first acoustic device may direct an acoustic signal in a direction. Further, the electronic device may include a camera to capture an image of an area in front of the electronic device. Furthermore, the electronic device may include a processor operatively coupled to the camera and the first acoustic device. The processor may determine a location of a facial feature of an operator using the captured image. Further, the processor may control an angle of rotation of the first acoustic device relative to the housing based on the location of the facial feature to modify the direction of the acoustic signal.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 7, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chih-Hua Chen, Cheng-Yi Yang, Hai-Lung Hung
  • Patent number: 11581628
    Abstract: An antenna structure includes a first radiator, a second radiator, an antenna ground, and a conductor. The first radiator for resonating at a high frequency band includes a feeding end. The second radiator is connected to the first radiator and resonates at a low frequency band with a part of the first radiator. The antenna ground is located on one side of the first radiator and the second radiator. The conductor is located between the second radiator and the antenna ground in a first direction and connected to the first radiator and the antenna ground. A slit having at least one bending portion is formed among the second radiator, and the conductor and the antenna ground. An electronic device is further provided.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 14, 2023
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Shih-Keng Huang, Chao-Hsu Wu, Yi-Ru Yang, Ching-Hsiang Ko, Cheng-Hsiung Wu, Ming-Huang Chen
  • Patent number: 11569236
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Publication number: 20230015761
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi LEE, Cheng-Lung HUNG, Ji-Cheng CHEN, Weng CHANG, Chi On CHUI
  • Patent number: 11552066
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Ming Wu, Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20230004035
    Abstract: A display device, characterized in that the display device includes a first panel having a first side and a first light shielding layer at a periphery of the first panel, wherein the first light shielding layer has a first edge departing away from the first side; and a second panel, disposed on the first panel, and having a second side adjacent to the first side; wherein the second panel includes a second light shielding layer at a periphery of the second panel; and the second light shielding layer has a second edge departing away from the second side. Wherein a first width is measured from the first side to the first edge along a direction, a second width is measured from the second side to the second edge along the direction, the second width is greater than the first width, and the direction is vertical to the first side.
    Type: Application
    Filed: August 30, 2022
    Publication date: January 5, 2023
    Inventors: Chien-Hung CHAN, Jin-Yi TAN, Cheng-Tso HSIAO, Huang-Chi CHAO, Ming-Feng HSIEH, Ying-Jen CHEN
  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Publication number: 20220413600
    Abstract: In an example, an electronic device may include a housing and a first acoustic device pivotally disposed in the housing. The first acoustic device may move between a first position within the housing and a second position outside the housing. The first acoustic device may direct an acoustic signal in a direction. Further, the electronic device may include a camera to capture an image of an area in front of the electronic device. Furthermore, the electronic device may include a processor operatively coupled to the camera and the first acoustic device. The processor may determine a location of a facial feature of an operator using the captured image. Further, the processor may control an angle of rotation of the first acoustic device relative to the housing based on the location of the facial feature to modify the direction of the acoustic signal.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Chih-Hua CHEN, Cheng-Yi Yang, Hai-Lung Hung
  • Publication number: 20220392799
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Chung-Lei CHEN, Cheng-Hsin CHEN, Chung Chieh TING, Che-Yi LIN, Clark LEE
  • Publication number: 20220380745
    Abstract: Provided is a non-naturally occurring microorganism capable of producing cadaverine, wherein the microorganism is genetically modified to overexpress lysine decarboxylase and pyridoxal kinase. Also provided is a method for producing cadaverine by using such microorganism without adding external pyridoxal 5?-phosphate.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: CHINA PETROCHEMICAL DEVELOPMENT CORPORATION, TAIPEI (TAIWAN)
    Inventors: Jo-Shu CHANG, I-Son NG, Cheng-Feng XUE, Ying-Jung CHEN, Chang-Yi CHEN, Yu-Chiao LIU
  • Patent number: 11508710
    Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
  • Publication number: 20220362887
    Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20220367565
    Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
    Type: Application
    Filed: June 11, 2021
    Publication date: November 17, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
  • Patent number: 11497748
    Abstract: The present invention relates to adenine which is useful to activate AMP-activated protein kinase (AMPK) and the use of adenine in the prevention or treatment of conditions or disease and thereby prevent or treat conditions or diseases which can be ameliorated by AMPK in a mammal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 15, 2022
    Assignee: Energenesis Biomedical Co., Ltd.
    Inventors: Han-Min Chen, Cheng-Yi Kuo, Chun-Fang Huang, Jiun-Tsai Lin
  • Publication number: 20220356342
    Abstract: A resin composition is provided, which includes a first polymer and a second polymer. The first polymer is formed by a reaction of an epoxy resin modified with a first elastic molecular segment and an epoxy resin curing agent. The second polymer is formed by a polymerization of an acrylate modified with a second elastic molecular segment.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Yi LIN, Shih-Ming CHEN
  • Publication number: 20220359236
    Abstract: The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Yen-Ji CHEN, Chih-Shen YANG, Cheng-Yi HUANG
  • Patent number: 11494475
    Abstract: The invention provides a safety system for a cleanroom, which comprises a cleanroom garment provided with a plurality of RFID (radio frequency identification) tags, a face recognition device arranged at an entrance of the cleanroom, and a first RFID reader arranged beside at least one machine in the cleanroom, wherein the first RFID reader is used for identifying the RFID tags on the cleanroom garment, and a KVM network power interrupter connected to a display screen of the machine.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 8, 2022
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Chao Wu, Chung-Li Chien, Cheng-Tar Lu, Zi Xin Chen, Sheng Kai Wang, Wen Yi Tan
  • Patent number: 11496048
    Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 8, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ming-Wei Chou, Sheng-Jian Chen, Chia-Chang Hsu, Cheng-Yi Lo