Patents by Inventor Cheng-Yi Chen

Cheng-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240122078
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11951569
    Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240088267
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
  • Publication number: 20240087917
    Abstract: The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Ji CHEN, Chih-Shen YANG, Cheng-Yi HUANG
  • Publication number: 20230357231
    Abstract: The present invention relates to crystalline forms of a KRas G12C inhibitor and salt thereof. In particular, the present invention relates to crystalline forms of the KRas GT2C inhibitor 2-[(2S)-4-[7-(8-chloro-1-naphthyI)-2-[[(2S)-1-methylpyrrolidin-2-yl]methoxy]-6,8-dihydro-5H-pyrido[3,4-d]pyrimidin-4-yI]-1-(2-fluoroprop-2-enoyi)piperazin-2-yl]acetonitrile, pharmaceutical compositions comprising the crystalline forms, processes for preparing the crystalline forms and methods of use thereof.
    Type: Application
    Filed: September 10, 2021
    Publication date: November 9, 2023
    Inventors: Patricia Andres, Samuel Andrew, Cheng Yi Chen, Susana Del Rio Gancedo, Tawfik Gharbaoui, Jennifer Nelson
  • Publication number: 20220289754
    Abstract: Processes for preparing (((3aR,6aS)-5-(4,6-dimethylpyrimidin-2-yl)hexahydropyrrolo[3,4-c]pyrrol-2(1H)-yl)(2-fluoro-6-(2H-1,2,3-triazol-2-yl)phenyl)methanone are described, which are useful for commercial manufacturing. Said compound is an orexin receptor modulator and may be useful in pharmaceutical compositions and methods for the treatment of diseased states, disorders, and conditions mediated by orexin activity, such as insomnia and depression.
    Type: Application
    Filed: August 6, 2020
    Publication date: September 15, 2022
    Applicant: JANSSEN PHARMACEUTICA NV
    Inventors: DOMINIQUE PAUL M DEPRE, KIRAN MATCHA, FLORIAN DAMIEN MEDINA, PIETER WESTERDUIN, CHENG YI CHEN
  • Publication number: 20220220062
    Abstract: The present invention is directed to methods for the asymmetric synthesis of esketamine. The present invention is further directed to key intermediates in the asymmetric esketamine synthesis. In one embodiment, the invention is an asymmetric synthesis of esketamine comprising the conversion of (S)-2?-chloro-2-methoxy-3,4,5,6-5 tetrahydro-[1,1?-biphenyl]-3-yl carbamate to (S)-2?-chloro-1-isocyanato-6-methoxy-1,2,3,4-tetrahydro-1,1?-biphenyl.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 14, 2022
    Inventor: Cheng Yi CHEN
  • Publication number: 20220204516
    Abstract: Disclosed is a process for the preparation of certain intermediates, e.g. a process R for preparing a compound of formula (I) wherein, R1, R2 and X1 are as defined in the description, and which intermediate and processes are useful in the preparation of a BTK inhibitor, such as ibrutinib.
    Type: Application
    Filed: May 20, 2020
    Publication date: June 30, 2022
    Inventors: Philip James PYE, Andras HORVATH, Cheng Yi CHEN, Yuanyuan Yuan, Jinxiong SU, Shuo WANG, Simon Albert WAGSCHAL
  • Patent number: 11081415
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 3, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Publication number: 20210024461
    Abstract: The present invention is directed to processes for the preparation of esketamine. The present invention is further directed to processes for the resolution of S-ketamine from a racemic or enantiomerically enriched mixture of ketamine. The present invention is further directed to an (S)-CSA salt of S-ketamine, more particularly a monohydrate form of the (S)-CSA salt of S-ketamine; and to an (R)-CSA salt of R-ketamine.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Cheng Yi Chen, Oliver Floegel, Michael Justus, Adrian Maurer, Karl Reuter, Tobias Strittmatter, Tobias Wedel
  • Patent number: 10815196
    Abstract: The present invention is directed to processes for the preparation of esketamine. The present invention is further directed to processes for the resolution of S-ketamine from a racemic or enantiomerically enriched mixture of ketamine. The present invention is further directed to an (S)-CSA salt of S-ketamine, more particularly a monohydrate form of the (S)-CSA salt of S-ketamine; and to an (R)-CSA salt of R-ketamine.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 27, 2020
    Assignee: Janssen Pharmaceutica NV
    Inventors: Cheng Yi Chen, Oliver Floegel, Michael Justus, Adrian Maurer, Karl Reuter, Tobias Strittmatter, Tobias Wedel
  • Publication number: 20200258802
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Patent number: 10679914
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 9, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Publication number: 20190198807
    Abstract: Provided is a barrier film which includes an organo-silicon polymeric composition having Si3—N4 bonds and Si—OH bonds. The peak height of Si4—N4 bonds in an infrared absorption spectrum is represented by A, and the peak height of Si—OH bonds in the infrared absorption spectrum is represented by B; and a ratio of A to B is greater than 2.
    Type: Application
    Filed: December 25, 2018
    Publication date: June 27, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Wen-Hung Liu, Cheng-Yi Chen, Hao-Che Kao, Hsin-Chu Chen
  • Patent number: 10201086
    Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Cheng-Hsiang Liu, Chang-Lun Lu, Jun-Cheng Liao, Cheng-Yi Chen
  • Publication number: 20180282266
    Abstract: The present invention is directed to processes for the preparation of esketamine. The present invention is further directed to processes for the resolution of S-ketamine from a racemic or enantiomerically enriched mixture of ketamine. The present invention is further directed to an (S)-CSA salt of S-ketamine, more particularly a monohydrate form of the (S)-CSA salt of S-ketamine; and to an (R)-CSA salt of R-ketamine.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Applicant: Janssen Pharmaceutica NV
    Inventors: Cheng Yi Chen, Oliver Floegel, Michael Justus, Adrian Maurer, Karl Reuter, Tobias Strittmatter, Tobias Wedel
  • Publication number: 20180254232
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Application
    Filed: June 28, 2017
    Publication date: September 6, 2018
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Patent number: 10053466
    Abstract: A process for preparing a compound of structural Formula Ia: comprising Boc deprotection with TFA of: ?and reductive amination of:
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 21, 2018
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: John Y. L. Chung, Feng Peng, Yonggang Chen, Amude Mahmoud Kassim, Cheng-yi Chen, Mathew Maust, Mark McLaughlin, Michael J. Zacuto, Qinghao Chen, Lushi Tan, Zhiguo Jake Song, Yang Cao, Feng Xu
  • Patent number: 9991478
    Abstract: A method for fabricating an organic electro-luminescence device, comprising: forming a first conductive layer comprising a first electrode and a contact pattern on a substrate; forming a first mask on the first conductive layer, the first mask comprising an opening for exposing a portion of the first electrode and a portion of the contact pattern; forming a patterned organic functional layer by shielding of a second mask, the patterned organic functional layer covering the first mask and the first electrode exposed by the first mask, and the second mask being disposed over the first mask to shield the portion of the contact pattern exposed by the opening; forming a second conductive layer and patterning the second conductive layer by removing the first mask and a portion of the second conductive layer on the first mask to form a second electrode electrically connected to the contact pattern.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: June 5, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Yi Chen, Chao-Feng Sung, Jyun-Kai Ciou, Yung-Min Hsieh