Patents by Inventor Cheng-Yi Hsu
Cheng-Yi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122078Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Publication number: 20230112479Abstract: The present invention provides a photodiode, which includes: a light absorption substrate, a first electrode portion, a second electrode portion, an antireflection layer, and a distributed Bragg reflection layer. The antireflection layer is arranged to receive light to get into the light absorption substrate. The antireflection layer is arranged to receive light to get into the light absorption substrate, and the distributed Bragg reflection layer is arranged to reflect light transmitting through the light absorption substrate to exit from the light absorption substrate back to the light absorption substrate, in order to enhance the photocurrent and the spectrum sensitivity of the photodiode.Type: ApplicationFiled: October 12, 2021Publication date: April 13, 2023Inventors: SHIH-KANG CHEN, CHIH-YANG CHANG, CHENG-YI HSU
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Publication number: 20220162884Abstract: An electric lock including a main base, a lock bolt, an elastic rod, a driving assembly, and a remote receiver is provided. The lock bolt is pivotally rotatably disposed on a top surface of the main base. The elastic rod is movably arranged in the main base and connected to a free end of the lock bolt. The driving assembly is disposed on a side of the main base and connected to the elastic rod. The remote receiver is coupled to the driving assembly. In a remote mode, the remote receiver is adapted to receive a signal to turn on the driving assembly, and the driving assembly drives the lock bolt through the elastic rod to rotate relative to the main base to switch to a locked state or an unlocked state.Type: ApplicationFiled: September 24, 2021Publication date: May 26, 2022Applicant: Eltronix Co. LtdInventors: Jen-Tsang Chen, Cheng-Yi Hsu
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Patent number: 11296821Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.Type: GrantFiled: March 2, 2020Date of Patent: April 5, 2022Assignee: MEDIATEK INC.Inventors: Chong-You Lee, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
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Patent number: 10958290Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.Type: GrantFiled: August 19, 2019Date of Patent: March 23, 2021Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee
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Patent number: 10832377Abstract: A calibration method for linking spherical coordinates to texture coordinates is provided. The method comprises: installing a plurality of lamps forming a horizontal semicircle arc and a rotation equipment located at its circle center; mounting a N-lens camera on the rotation equipment; causing the N-lens camera to spin about a spin axis passing through two ends of the horizontal semicircle arc and capture a plurality of lens images for different spin angles by the rotation equipment; and, determining longitude and latitude coordinates of a plurality of calibration points according to the different spin angles and the texture coordinates of the calibration points in the lens images to create a link between the spherical coordinates and the texture coordinates. Different positions of the lamps respectively represent different latitudes and different spin angles respectively represent different longitudes. Heights of the camera and the lamps are the same.Type: GrantFiled: January 4, 2019Date of Patent: November 10, 2020Assignee: ASPEED TECHNOLOGY INC.Inventors: Chung-Yen Lu, Cheng-Yi Hsu, Hsin-Yu Chen
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Patent number: 10790853Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.Type: GrantFiled: November 25, 2018Date of Patent: September 29, 2020Assignee: MEDIATEK INC.Inventors: Mao-Ching Chiu, Chong-You Lee, Cheng-Yi Hsu, Timothy Perrin Fisher-Jeffes, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
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Publication number: 20200219230Abstract: A calibration method for linking spherical coordinates to texture coordinates is provided. The method comprises: installing a plurality of lamps forming a horizontal semicircle arc and a rotation equipment located at its circle center; mounting a N-lens camera on the rotation equipment; causing the N-lens camera to spin about a spin axis passing through two ends of the horizontal semicircle arc and capture a plurality of lens images for different spin angles by the rotation equipment; and, determining longitude and latitude coordinates of a plurality of calibration points according to the different spin angles and the texture coordinates of the calibration points in the lens images to create a link between the spherical coordinates and the texture coordinates. Different positions of the lamps respectively represent different latitudes and different spin angles respectively represent different longitudes. Heights of the camera and the lamps are the same.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Chung-Yen LU, Cheng-Yi HSU, Hsin-Yu CHEN
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Publication number: 20200204295Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Applicant: MEDIATEK INC.Inventors: Chong-You LEE, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
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Patent number: 10659079Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.Type: GrantFiled: May 4, 2018Date of Patent: May 19, 2020Assignee: MEDIATEK INC.Inventors: Cheng-Yi Hsu, Chong-You Lee, Wei Jen Chen, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang
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Patent number: 10630319Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.Type: GrantFiled: January 23, 2018Date of Patent: April 21, 2020Assignee: MEDIATEK INC.Inventors: Ju-Ya Chen, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee
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Patent number: 10608665Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.Type: GrantFiled: March 9, 2018Date of Patent: March 31, 2020Assignee: MEDIATEK INC.Inventors: Chong-You Lee, Timothy Perrin Fisher-Jeffes, Maoching Chiu, Wei Jen Chen, Cheng-Yi Hsu, Ju-Ya Chen, Yen Shuo Chang
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Patent number: 10601544Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.Type: GrantFiled: February 5, 2018Date of Patent: March 24, 2020Assignee: MEDIATEK INC.Inventors: Chong-You Lee, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
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Patent number: 10581457Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.Type: GrantFiled: January 5, 2018Date of Patent: March 3, 2020Assignee: MEDIATEK INC.Inventors: Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
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Patent number: 10567116Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.Type: GrantFiled: May 31, 2018Date of Patent: February 18, 2020Assignee: MEDIATEK INC.Inventors: Mao-Ching Chiu, Chong-You Lee, Timothy Perrin Fisher-Jeffes, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
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Publication number: 20190372600Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee
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Patent number: 10432227Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.Type: GrantFiled: January 23, 2018Date of Patent: October 1, 2019Assignee: MEDIATEK INC.Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee