Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.

Abstract: An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. The at least one dummy pattern is disposed on the substrate and located adjacent to the alignment mark, wherein a size of the at least one dummy pattern is smaller than a size of the alignment mark.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireless network. In encoding the data, the processor encodes the data with a low-density parity-check (LDPC) code to provide LDPC-coded data. Moreover, the processor processes the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data. The FEC robustness enhancement function includes an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

Abstract: An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. The at least one dummy pattern is disposed on the substrate and located adjacent to the alignment mark, wherein a size of the at least one dummy pattern is smaller than a size of the alignment mark.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.

Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

Abstract: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed so as to improve the heat dissipation efficiency of the light-emitting device.

Abstract: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed so as to improve the heat dissipation efficiency of the light-emitting device.

Abstract: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed so as to improve the heat dissipation efficiency of the light-emitting device.

Abstract: A thermometer includes a circuit board disposed in a housing, a detector attached to the circuit board for detecting a temperature signal of a user, a processor device attached to the circuit board and electrically coupled to the detector for receiving the detected temperature signal of the user from the detector, and a displayer attached to the circuit board and electrically coupled to the processor device for displaying the detected temperature signal of the user. A warning device may be attached to the circuit board and electrically coupled to the processor device for generating a warning signal when the user is detected to be over-heated for allowing the user to be taken care of as early as possible.