Patents by Inventor Cheng-Yi Huang

Cheng-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367632
    Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Wen Wu, Chun-Ta Chen, Chin-Shen Hsieh, Cheng-Yi Huang
  • Publication number: 20220179521
    Abstract: The present invention discloses a noise reduction touch light adjustment device including a light adjustment film, a capacitive touch panel, a noise reduction film, a glass substrate, a control circuit module, and an alternating current (AC) transformer. The noise reduction film is disposed between the light adjustment film and the capacitive touch panel to lower noise inputted from the AC transformer into the light adjustment film such that the capacitive touch panel is ensured to be operated precisely.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Yi-Feng CHIANG, Cheng-Yi HUANG
  • Publication number: 20220101909
    Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: William Waller, Cheng-Yi Huang
  • Patent number: 11289311
    Abstract: A method and apparatus for dosage measurement and monitoring in an ion implantation system is disclosed. In one embodiment, a transferring system, includes: a vacuum chamber, wherein the vacuum chamber is coupled to a processing chamber; a shaft coupled to a ball screw, wherein the ball screw and the shaft are configured in the vacuum chamber; and a vacuum rotary feedthrough, wherein the vacuum rotary feedthrough comprises a magnetic fluid seal so as to provide a high vacuum sealing, and wherein the vacuum rotary feedthrough is configured through a first end of the vacuum chamber and coupled to the ball screw so as to provide a rotary motion on the ball screw.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Lin, Fang-Chi Chien, Cheng-Yi Huang, Chao-Po Lu
  • Patent number: 11270950
    Abstract: An apparatus and a method for forming alignment marks are disclosed. The method for forming alignment marks is a photolithography-free process and includes the following operations. A laser beam is provided. The laser beam is divided into a plurality of laser beams separated from each other. The plurality of laser beams is shaped into a plurality of patterned beams, so that the plurality of patterned beams is shaped with patterns corresponding to alignment marks. The plurality of patterned beams is projected onto a semiconductor wafer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chen Liu, Cheng-Hao Yu, Cheng-Yi Huang, Chao-Li Shih, Chih-Shen Yang
  • Publication number: 20210351048
    Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Kai-Wen WU, Chun-Ta CHEN, Chin-Shen HSIEH, Cheng-Yi HUANG
  • Patent number: 11121093
    Abstract: A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yue-Lin Peng, Cheng-Yi Huang, Fu-Jen Li, Shou-Wen Kuo
  • Patent number: 11075104
    Abstract: A semiconductor chuck is provided. The semiconductor chuck includes a metal base and a first adhesive layer over the metal base. The semiconductor chuck includes a dielectric layer over the first adhesive layer, wherein the dielectric layer is adhered to the metal base by the first adhesive layer. The semiconductor chuck includes a removable protective plate over the dielectric layer, wherein a first portion of the removable protective plate covers a top surface of the dielectric layer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Fu-Zen Lin, Chien-Hsiang Chen, Chih-Shen Yang, Hsu-Shui Liu, Cheng-Yi Huang
  • Publication number: 20210098390
    Abstract: An apparatus and a method for forming alignment marks are disclosed. The method for forming alignment marks is a photolithography-free process and includes the following operations. A laser beam is provided. The laser beam is divided into a plurality of laser beams separated from each other. The plurality of laser beams is shaped into a plurality of patterned beams, so that the plurality of patterned beams is shaped with patterns corresponding to alignment marks. The plurality of patterned beams is projected onto a semiconductor wafer.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chen Liu, Cheng-Hao Yu, Cheng-Yi Huang, Chao-Li Shih, Chih-Shen Yang
  • Patent number: 10966140
    Abstract: A method for detecting and preventing the operation of a rogue access point (AP) by issuing deauthentication packets thereto includes receiving beacon packets of all wireless APs in a wireless network area, obtaining timestamps, and establishing a clock skew model for each wireless AP accordingly. Each clock skew model can be held abnormal according to a growth slope of the clock skew model, and the wireless AP corresponding to an abnormal clock offset model can be defined as a rogue AP. Position and distance range of the rogue AP can be established by RSSIs, and a specified authorized AP adjacent to the rogue AP can be selected and controlled to send deauthentication packets to the rogue AP. A device for detecting and restraining the rogue AP is also provided.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 30, 2021
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventors: Cheng-Yi Huang, Chih-Wei Su
  • Publication number: 20210066054
    Abstract: A Faraday shield, a semiconductor processing apparatus, and an etching apparatus are provided. The Faraday shield includes a plurality of conductive slices and a spacer interposed between adjacent two of the conductive slices to electrically isolate the adjacent two of conductive slices from one another. The conductive slices are separately arranged aside one another and oriented along a circumference of the Faraday shield. A coil is wound around the circumference of the Faraday shield.
    Type: Application
    Filed: July 14, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsiang Chen, Ching-Horng Chen, Yen-Ji Chen, Cheng-Yi Huang, Chih-Shen Yang
  • Publication number: 20210066108
    Abstract: A semiconductor chuck is provided. The semiconductor chuck includes a metal base and a first adhesive layer over the metal base. The semiconductor chuck includes a dielectric layer over the first adhesive layer, wherein the dielectric layer is adhered to the metal base by the first adhesive layer. The semiconductor chuck includes a removable protective plate over the dielectric layer, wherein a first portion of the removable protective plate covers a top surface of the dielectric layer.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: Fu-Zen Lin, Chien-Hsiang Chen, Chih-Shen Yang, Hsu-Shui Liu, Cheng-Yi Huang
  • Publication number: 20200396671
    Abstract: A method for detecting and preventing the operation of a rogue access point (AP) by issuing deauthentication packets thereto includes receiving beacon packets of all wireless APs in a wireless network area, obtaining timestamps, and establishing a clock skew model for each wireless AP accordingly. Each clock skew model can be held abnormal according to a growth slope of the clock skew model, and the wireless AP corresponding to an abnormal clock offset model can be defined as a rogue AP. Position and distance range of the rogue AP can be established by RSSIs, and a specified authorized AP adjacent to the rogue AP can be selected and controlled to send deauthentication packets to the rogue AP. A device for detecting and restraining the rogue AP is also provided.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: CHENG-YI HUANG, CHIH-WEI SU
  • Publication number: 20200287100
    Abstract: Disclosed herein are a light-emitting diode (LED) package structure and a method producing the same. The LED package structure includes a substrate; and a light-emitting unit disposed on the substrate. The light-emitting unit comprises a gallium nitride-based semiconductor, and a polymeric layer encapsulating the gallium nitride-based semiconductor. Also disclosed herein is a method of producing the LED package structure. The method comprises: providing a substrate; electrically connecting a gallium nitride-based semiconductor onto the substrate; overlaying the gallium nitride-based semiconductor with a slurry comprising a resin and a plurality of composite fluorescent gold nanocluster; and curing the slurry overlaid on the gallium nitride-based semiconductor to form a solidified polymeric layer.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Applicant: Chung Yuan Christian University
    Inventors: Cheng-An LIN, Yeeu-Chang LEE, Cheng-Yi HUANG, Chi-An CHEN, Yi-Tang SUN
  • Patent number: 10752834
    Abstract: Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 25, 2020
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Cheng-An Lin, Cheng-Yi Huang, Chia-Hui Lin, Tzu-Yin Hou
  • Patent number: 10756243
    Abstract: Disclosed herein are a light-emitting diode (LED) package structure and a method producing the same. The LED package structure includes a substrate; and a light-emitting unit disposed on the substrate. The light-emitting unit comprises a gallium nitride-based semiconductor, and a polymeric layer encapsulating the gallium nitride-based semiconductor. Also disclosed herein is a method of producing the LED package structure. The method comprises: providing a substrate; electrically connecting a gallium nitride-based semiconductor onto the substrate; overlaying the gallium nitride-based semiconductor with a slurry comprising a resin and a plurality of composite fluorescent gold nanocluster; and curing the slurry overlaid on the gallium nitride-based semiconductor to form a solidified polymeric layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 25, 2020
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Cheng-An Lin, Yeeu-Chang Lee, Cheng-Yi Huang, Chi-An Chen, Yi-Tang Sun
  • Publication number: 20200192225
    Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 18, 2020
    Inventors: Ming-Hsuan CHUANG, Po-Sheng LU, Shou-Wen KUO, Cheng-Yi HUANG, Chia-Hung CHU
  • Publication number: 20200176269
    Abstract: In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 4, 2020
    Inventors: Hsing-Hsiang WANG, Yu-Hsiang LIN, Wei-Da CHEN, Tom PENG, P.Y CHIU, Miau-Shing TSAI, Cheng-Yi HUANG, Ching-Horng CHEN
  • Patent number: 10671108
    Abstract: A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. The bandgap core component includes a reference point having a voltage associated with an output signal of the output component. A controller is configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point. When the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption. When the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 2, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Josh Yang, Zhi Bing Deng, Cheng Tai Huang, Cheng Yi Huang, Wen Jun Weng, Jun Tao Guo
  • Publication number: 20200168484
    Abstract: The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench.
    Type: Application
    Filed: June 3, 2019
    Publication date: May 28, 2020
    Inventors: Yen-Ji Chen, Chih-Shen Yang, Cheng-Yi Huang