Patents by Inventor Cheng You

Cheng You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100298952
    Abstract: Disclosed is a self-expanding medical implant for placement within a lumen of a patient. The implant comprises a woven or non-woven structure having a substantially tubular configuration, and is designed to be low-profile such that it is deliverable with a small diameter catheter. The implant has a high recoverability and desired mechanical properties.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Inventors: Rany Busold, Chang Cheng You, Daniel Concagh, Lee Core, Kicherl Ho, Maria Palasis, Upma Sharma, Greg Zugates
  • Publication number: 20100021960
    Abstract: Compositions, methods and related apparatus, as can be used for selective pathogen detection and identification.
    Type: Application
    Filed: November 17, 2008
    Publication date: January 28, 2010
    Inventors: Vincent Rotello, Uwe Bunz, Ronnie Phillips, Oscar Miranda, Chang-Cheng You
  • Publication number: 20090221099
    Abstract: Compositions, methods and related apparatus, as can be used for selective protein detection and identification.
    Type: Application
    Filed: November 17, 2008
    Publication date: September 3, 2009
    Inventors: Vincent Rotello, Uwe Bunz, Chang-Cheng You, Oscar Miranda, Ik-Bum Kim
  • Publication number: 20070190288
    Abstract: A multi-layered colored paper includes at least three layers of different colored papers. Each layer has a preset area with fibers on its surface intertwining with those of another neighboring layer. At first the three layers are superposed on one another in a half dried condition, letting the half wet fibers intertwined with one another not stably. After dried, the fibers of two neighboring layers intertwine stably with one another so that the three layers may be easily peeled off from each other, and not to move, slide or shift from each other during engraving.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 16, 2007
    Inventor: Tai-Cheng You
  • Patent number: 7159995
    Abstract: A display device and light source thereof. The light source is disposed in a housing. An electrode is connected to the light source. A first connecting portion having a first threaded surface is connected to the electrode. A second connecting portion having a second threaded surface is connected to an electric wire. The first threaded surface is electrically connected to the second threaded surface to connect the electric wire and the light source.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: January 9, 2007
    Assignee: AU Optronics Corp.
    Inventors: Kai-Yu Sun, Cheng-You Liu
  • Patent number: 7131750
    Abstract: A backlight apparatus includes a plurality of support members that maintain a diffuser plate in a fixed and level position with respect to the lamps and the housing that contains the lamps, to produce uniform illumination. The support members extend from the diffuser plate disposed at an open face of the housing, to the opposed back part of the housing, and include male-female interlocking parts to provide support. The support members include a set of cooperating portions, an upper and lower portion. The upper and lower portions may combine to provide a cavity in the support member. A cold cathode fluorescent lamp may extend through the cavity and the upper and lower portions may be secured to the diffuser plate and housing, respectively, by extending through openings formed in the diffuser plate or housing.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: November 7, 2006
    Assignee: AU Optronics Corporation
    Inventors: Cheng-You Liu, Kai-Yu Sun
  • Publication number: 20060136327
    Abstract: The invention provides a method for assessing risk within an organization, comprising: defining one or more zones (2), each of the one or more zones comprising an environment; identifying one or more assets (4) of the organization, each of the assets being located in a respective one of the zones; conducting a respective impact assessment (6) for each of the assets, each assessment comprising assessing the impact of the loss of the respective asset; conducting for each of the zones a respective zone risk assessment (8a), comprising assessing the risk level associated with placing a respective asset within the respective corresponding zone; and conducting for each asset a respective asset risk assessment (8b), comprising assessing the risk level associated with the respective asset independent of the respective zone of the respective asset; and assessing risk on the basis of at least the impact assessment, the zone risk assessments and the asset risk assessments.
    Type: Application
    Filed: July 1, 2003
    Publication date: June 22, 2006
    Inventor: Cheng You
  • Publication number: 20060023472
    Abstract: A backlight apparatus includes a plurality of support members that maintain a diffuser plate in a fixed and level position with respect to the lamps and the housing that contains the lamps, to produce uniform illumination. The support members extend from the diffuser plate disposed at an open face of the housing, to the opposed back part of the housing, and include male-female interlocking parts to provide support. The support members include a set of cooperating portions, an upper and lower portion. The upper and lower portions may combine to provide a cavity in the support member. A cold cathode fluorescent lamp may extend through the cavity and the upper and lower portions may be secured to the diffuser plate and housing, respectively, by extending through openings formed in the diffuser plate or housing.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Cheng-You Liu, Kai-Yu Sun
  • Publication number: 20050276049
    Abstract: A display device and light source thereof. The light source is disposed in a housing. An electrode is connected to the light source. A first connecting portion having a first threaded surface is connected to the electrode. A second connecting portion having a second threaded surface is connected to an electric wire. The first threaded surface is electrically connected to the second threaded surface to connect the electric wire and the light source.
    Type: Application
    Filed: September 13, 2004
    Publication date: December 15, 2005
    Inventors: Kai-Yu Sun, Cheng-You Liu
  • Patent number: 6717220
    Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: April 6, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tao Cheng, Jyh-Cheng You, Lin-June Wu
  • Publication number: 20030017673
    Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.
    Type: Application
    Filed: September 6, 2002
    Publication date: January 23, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Tao Cheng, Jyh-Cheng You, Lin-June Wu
  • Patent number: 6465308
    Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: October 15, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tao Cheng, Jyh-Cheng You, Lin-June Wu
  • Patent number: 6297102
    Abstract: The invention provides a method for forming a ROM cell surface implant region using a PLDD implant. A semiconductor structure is provided comprising a substrate having isolation structures thereon, which separate and electrically isolating a first area having a P-well formed in the substrate and a gate over the substrate, a second area having a N-well formed in the substrate and a gate over the substrate, and a third area having P-well and buried N+ regions formed in the substrate with second isolation structures overlying the buried N+ regions. A photoresist mask is formed exposing the first area, and impurity ions are implanted to form n-type lightly doped source and drain regions. The photoresist mask is removed and a new (PLDD/ROM) photoresist mask is formed exposing the second area and the third area. Impurity ions are implanted to simultaneously form p-type lightly doped source and drain regions and a ROM cell surface implant region region. The PLDD/ROM photoresist mask is then removed.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: October 2, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Cheng You, Lin-June Wu
  • Patent number: 6161053
    Abstract: A method and means for testing binary code devices, such as ROMs, for correct coding during processing with the Process Control Machine (PCM) for the fabrication process by applying it on the scribe-line built-in binary code devices, and using the testing program to measure the threshold voltage VTN of the code devices and convert the binary signal sensed to a decimal number to identify the ROM code id. After finishing wafer processing and PCM testing, the real ROM code id that has been fabricated can be read from the PCM testing report.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: December 12, 2000
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsin Pai Chen, Shaw Teung Yu, Jyh Cheng You, Wei Kun Yeh
  • Patent number: 6077746
    Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: June 20, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Cheng You, Lin-June Wu
  • Patent number: 6020241
    Abstract: The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: February 1, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Cheng You, Pei-Hung Chen, Shau-Tsung Yu, Yi-Jing Chu
  • Patent number: 5453725
    Abstract: An overcurrent breaker switch includes an upper housing including a lever block with a push rod and a lower housing engaged with the upper housing. First and second blades are mounted to the lower housing, the second blade having a dual metal plate mounted thereon. A lever plate base is mounted in the lower housing and has a first end for releasable electrical connection with the dual metal plate and a second end. A conductive lever plate is pivotally mounted to the second end of the lever plate base and actuatable by the push rod under operation of the lever block. The conductive lever plate has a first end for releasable electrical connection with the first blade and a second end on which a pressing piece is formed. An insulating plate is mounted between the lever plate base and the dual metal plate and has an insulating piece below the pressing piece of the conductive lever plate. A spring is mounted under the insulating piece to provide an upward force.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: September 26, 1995
    Inventors: Long-Cheng You, Shou-Chi Kuo