Abstract: A computer processing system is provided for enhancing video-based language learning. The system includes a video server for storing videos that use one or more languages to be learned. The system further includes a video metadata database for storing translations of sentences uttered in the videos, character profiles of characters appearing in the videos, and mappings between the sentences and a learner profile. The system also includes a learner profile database for storing learner profiles. The system additionally includes a semantic analyzer and matching engine for finding, for at least a given video and a given learner, alternative sentences for and responsive to the translations of the sentences uttered in the given video that conflict with a respective learner profile for the given learner. The computer processing system further includes a presentation system for playing back the given video and providing the alternative sentences to the given learner.

Abstract: Provided is a construction method for a fully prefabricated multi-story concrete plant, the construction method may achieve full coverage of a hoisting operation of the large beam and column prefabricated components of a floor by employing a single intelligent hoisting robot, an angle change of the track devices, an angle change of a moving device, and a self-lifting device. It is not necessary to arrange a transition track at the turn of the installation route, which saves space and installation cost, and overcomes the disadvantage of high cost caused by the traditional prefabricated construction mode of multi-story concrete plant, which needs to arrange a plurality of large hoisting equipment. It may achieve the mechanization and intelligence of the whole construction process of the fully prefabricated multi-story concrete plant.

Abstract: A semiconductor device includes a first oxide layer and a gate structure. The first oxide layer is disposed on a substrate. The gate structure is disposed on the first oxide layer. The gate structure includes a gate and a spacer surrounding the gate. The first oxide layer includes an exposed segment not covered by the gate structure. A thickness of the first oxide layer right below the gate is fixed, and the thickness of the first oxide layer right below the gate is greater than a thickness of the exposed segment.

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

Abstract: An optical imaging lens assembly includes seven lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The second lens element has negative refractive power. The object-side surface of the third lens element is concave in a paraxial region thereof. The fourth lens element has positive refractive power. The image-side surface of the fifth lens element is concave in a paraxial region thereof. The sixth lens element has positive refractive power, and the image-side surface of the sixth lens element is convex in a paraxial region thereof.

Abstract: A semiconductor device, and method of fabricating the same, includes a first substrate, the first substrate including at least one visible light photosensor disposed between a first side and a second side of the first substrate, a second substrate including an infrared light photosensor disposed between a second side of the second substrate and a first side of the second substrate, and a metalens disposed between the visible light photosensor and the infrared light photosensor, the metalens configured to focus infrared light impinging on a surface of the first substrate onto the infrared light photosensor.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: A voltage meter includes a sampler, a gain circuit, an accumulator and a feedback circuit. The sampler samples an input signal to generate a series of first signals and a series of second signals. The gain circuit, coupled to the sampler, modifies at least one of the series of first signals and the series of second signals, to generate a series of modified first signals and a series of modified second signals. The accumulator, coupled to the gain circuit, accumulates an operational result of the series of modified first signals and the series of modified second signals, to generate an accumulation result. The feedback circuit, coupled between the accumulator and the sampler, sends a feedback signal back to the sampler according to the accumulation result.

Abstract: A harmonic suppression method and apparatus for a three-phase three-wire cascaded power conversion apparatus is disclosed.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.

Abstract: Provided is a direct current voltage sampling circuit used for a medium-voltage power module. The medium-voltage power module includes two cascaded H-bridge circuits. The sampling circuit includes two sampling sub-circuits, with each connected to one H-bridge circuit. The sampling sub-circuit includes: a voltage dividing circuit connected in parallel to an output end of the H-bridge circuit, an isolation module connected to the voltage dividing circuit, a direct current isolated power supply which supplies power to the isolation module independently of the H-bridge circuit, and an amplifier conditioning module which converts an isolated voltage signal into a sampled voltage output. Parasitic capacitances of the isolation module and the direct current isolated power supply are both less than 2 pF, and the sampled voltage outputs of the two sampling sub-circuits are provided to a same local controller.

Abstract: A cable assembly, configured to be mounted to a circuit board having a first conductive pad and a second conductive pad, includes a first cable, a second cable and a support member. The first cable includes a first core, a first insulator and a first shielding layer. The second cable includes a second core, a second insulator and a second shielding layer. The first core and the second core are configured to be in contact with the first conductive pad and the second conductive pad. The support member includes a support portion. The support portion is configured to support the first insulator and the second insulator. The connection portion is in contact with the first shielding layer and the second shielding layer. A cable connector having the cable assembly is also disclosed.

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

Abstract: A uniform temperature plate comprises a first plate, a second plate, and a braided wire. The second plate is enclosed with the first plate to form a containing cavity. The containing cavity is filled with working liquid. The containing cavity comprises an evaporation zone and a condensation zone. The braided wire has a capillary structure is arranged in the containing cavity. A first end of the braided wire is arranged in the evaporation zone. A second end of the braided wire is arranged in the condensation zone. Through the capillary structure of the braided wire, the evaporating and re-cooling working liquid can be diverted to the evaporation zone quickly, so as to avoid water accumulated in the uniform temperature plate, improve the reflux efficiency and the temperature uniform performance of the uniform temperature plate. An electronic equipment is also provided.

Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.

Abstract: This disclosure relates to methods, devices and systems for real-time recognition of restoration of spontaneous circulation (ROSC) in cardio-pulmonary resuscitation (CPR) process. Recognition mechanisms in both time domain and frequency domain are provided for the ROSC recognition, where the time-domain recognition logic may detect the ROSC by recognizing envelope features of sampled signals in the time domain, and the frequency-domain recognition logic may detect the ROSC by recognizing spectral peaks at different frequency points continuously or significant variations of amplitude of spectral peaks in the frequency spectrum.

Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.