Patents by Inventor Cheng Yu

Cheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332560
    Abstract: An electrochemical cell stack includes electrochemical cells that each contain a fuel electrode, an air electrode and an electrolyte disposed therebetween, interconnects disposed between the electrochemical cells, and an interconnect end plate disposed over the fuel electrode of an outermost one of the electrochemical cells. The interconnect end plate includes a fuel side, an opposing air side, fuel ribs disposed on the fuel side and at least partially defining fuel channels, air ribs disposed on the air side and at least partially defining dummy air channels, fuel holes extending from the fuel side to the air side, and recessed ring seal regions disposed on the air side surrounding the fuel holes.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Michael REISERT, Richard A. VILLA, Cheng-Yu LIN, Khuzema KHAIRULLAH, Tad ARMSTRONG, Harald HERCHEN, Christopher LEE
  • Publication number: 20240332174
    Abstract: An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Cheng-Yu LIN, Jung-Chan YANG, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Kuo-Nan YANG, Chih-Liang CHEN, Lee-Chung LU
  • Publication number: 20240332561
    Abstract: A fuel cell interconnect includes an air side and an opposing fuel side, air ribs disposed on the air side and at least partially defining air channels, and fuel ribs disposed on the fuel side and a least partially defining fuel channels. The fuel channels include central fuel channels disposed in a central fuel field, the central fuel channels having a cross-sectional area A1, peripheral fuel channels disposed in peripheral fuel fields that are disposed on opposing sides of the central fuel field, the peripheral fuel channels having a cross-sectional area A3, and intermediate fuel channels disposed in intermediate fuel fields that are disposed between the central fuel field and the peripheral fuel fields, the intermediate fuel channels having a cross-sectional area A2, where area A1<area A2<area A3.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Cheng-Yu LIN, Sachin PARHAR, Annamalai RAMAN, Sagar BONE
  • Publication number: 20240332332
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.
    Type: Application
    Filed: June 5, 2024
    Publication date: October 3, 2024
    Inventors: Cheng Yu Huang, Wei-Chieh Chiang, Keng-Yu Chou, Tzu-Hsuan Hsu
  • Publication number: 20240332026
    Abstract: A substrate grinding tool is configured to remove material from a semiconductor substrate in a grinding operation. In the grinding operation, the substrate grinding tool uses a combination of mechanical grinding and a chemical etchant to remove material from the semiconductor substrate. The chemical etchant may be heated to a high temperature, which may increase the etch rate of the chemical etchant. The use of the combination of mechanical grinding and the chemical etchant may increase the grinding rate of the substrate grinding tool for grinding semiconductor substrates, may reduce surface roughness for semiconductor substrates that are processed by the substrate grinding tool, and/or may reduce surface damage for semiconductor substrates that are processed by the substrate grinding tool, among other examples.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 3, 2024
    Inventors: Chi-Fan CHEN, Chun-Kai LAN, Zhen Yu GUAN, Hsun-Chung KUANG, Cheng-Yuan TSAI, Chung-Yi YU
  • Publication number: 20240332169
    Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Pei-Yu Wang, Cheng-Ting Chung, Wei Ju Lee
  • Patent number: 12107343
    Abstract: An antenna structure includes a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a switch circuit. The feeding radiation element has a feeding point. The second radiation element is coupled through the first radiation element to the feeding radiation element. The third radiation element is coupled to the second radiation element. The fourth radiation element is coupled to the second radiation element. The fourth radiation element and the third radiation element extend in different directions. The fifth radiation element has a tuning point, and is coupled to the feeding radiation element. The feeding radiation element is disposed between the first radiation element and the fifth radiation element. The switch circuit selectively couples the tuning point to a ground voltage.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 1, 2024
    Assignee: WISTRON CORP.
    Inventors: Cheng-Chieh Yang, Chih-Ming Chen, Po-Yu Chen
  • Patent number: 12106969
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 1, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Mukta Ghate Farooq, Julien Frougier, Takeshi Nogami, Roy R. Yu, Kangguo Cheng
  • Patent number: 12103969
    Abstract: Disclosed herein is a novel monoclonal antibody exhibiting binding affinity to Siglec-3 receptor. According to the embodiment, the monoclonal antibody is capable of reversing HBV-induced immunosuppression. Accordingly, also disclosed herein are the uses thereof in the treatment and/or prophylaxis of hepatitis B virus (HBV) infection.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 1, 2024
    Assignee: Academia Sinica
    Inventors: Shie-Liang Hsieh, Tsung-Yu Tsai, An-Suei Yang, Chung-Ming Yu, Cheng-Yuan Peng
  • Patent number: 12107423
    Abstract: A method and system for supplying power at a voltage selected from a plurality of voltages. Power is initially received at a first voltage. Embodiments communicate with an AC adapter to get device identification and see if the AC adapter supports other voltages. If so, embodiments communicate with the AC adapter to get more information about the adapter and identify what voltages the adapter is capable of providing. If one of the voltages would allow an information handling system to operate more efficiently, embodiments negotiate a power supply contract to operate at a second voltage. When the information handling system powers down, the system resets to operation at the initial voltage.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products L.P.
    Inventors: Wei-Cheng Yu, Merle Jackson Wood, Tsung-Cheng Liao, Chin-Jui Liu, Andrew Thomas Sultenfuss, Chi Che Wu
  • Patent number: 12107131
    Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240320821
    Abstract: Methods and apparatus for detecting plant disease in an area, the apparatus including a memory storing instructions and at least one processor configured to execute the instructions to perform operations including obtaining a red-green-blue (RGB) aerial image of the area and a multispectral aerial image of the area containing image data in red, green, blue, red edge, and near-infrared bands; detecting a plurality of plants in the area based on the RGB aerial image of the area; determining a plurality of vegetation indices respectively corresponding to the plurality of plants based on the multispectral aerial image of the area; and determining whether plant disease exists in the plurality of plants respectively based on the plurality of vegetation indices and a disease threshold.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Cheng-Fang LO, Kuang-Yu CHEN
  • Publication number: 20240322013
    Abstract: A method for manufacturing a semiconductor structure includes forming first and second channel layers over a substrate, forming first source/drain features over the first and second channel layers, forming a gate dielectric layer wrapping around the first and second channel layers, forming a first work function layer wrapping around the gate dielectric layer, forming a hard mask layer wrapping around the first work function layer, removing portions of the hard mask layer and the first work function layer, removing the hard mask layer and the first work function layer wrapping around the second channel layer, removing the hard mask layer wrapping around the first channel layer, forming a second work function layer wrapping around the first work function layer and the second channel layer, forming a metal material between the second work function layer, and forming second source/drain features under the first and second channel layers.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fu LU, Chih-Hao Wang, Wang-Chun Huang, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Publication number: 20240320830
    Abstract: Methods and apparatus for detecting plant disease in an area, the apparatus including a memory storing instructions and at least one processor configured to execute the instructions to perform operations including: obtaining a plurality of multispectral aerial images corresponding to a plurality of plants, obtaining one or more template images of one or more sample plants, and determining whether plant disease exists in the plurality of plants based on the multispectral aerial images and the one or more template images.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Cheng-Fang LO, Kuang-Yu CHEN
  • Publication number: 20240321858
    Abstract: A semiconductor device includes a semiconductor layer, a deep trench isolation structure, a shallow trench isolation structure, a first resistance layer, a second resistance layer, a first heavily doped region, a second heavily doped region, and a conductive line. The deep trench isolation structure separates the semiconductor device into a plurality of units including the first and second units. The shallow trench isolation structure is disposed on a portion of the semiconductor layer in one of the plurality of units. The first and second resistance layers are disposed on the shallow trench isolation structure in the first and second units respectively. The first and second heavily doped regions are embedded in the shallow trench isolation structure and in physical contact with the semiconductor layer in the first and second units respectively. The conductive line electrically connects the first and second resistance layers and the second heavily doped region.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Cheng-Yu WANG
  • Publication number: 20240322041
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 26, 2024
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 12100720
    Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Patent number: 12099730
    Abstract: A data storage system with intelligent power management includes a plurality of data storage devices and a controller. Each data storage device is capable of operating in one of (N+1) power saving functions where N is an integer larger than 1. The (N+1) power saving functions sequentially correspond to from the 0th to the Nth power saving levels. The controller reads a user-setting power saving level (I) where I is an integer index ranging from 0 to N. The controller reads a current power saving level (J) of a current power saving function of one of the plurality of data storage devices where J is an integer index ranging from 0 to N. The controller controls said one data storage device to operate in one power saving function among the (N+1) power saving functions according to the user-setting power saving level (I) and the current power saving level (J).
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: September 24, 2024
    Assignee: PROMISE TECHNOLOGY, INC.
    Inventors: Zhi-Yu Wu, Cheng-Chou Wang, Che-Jen Wang
  • Patent number: 12098477
    Abstract: The present disclosure provides a manufacturing method of semi-insulating single-crystal silicon carbide powder comprising: providing a semi-insulating single-crystal silicon carbide bulk, wherein the semi-insulating single-crystal silicon carbide bulk has a first silicon-vacancy concentration, and the first silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}?3; refining the semi-insulating single-crystal silicon carbide bulk to obtain a semi-insulating single-crystal silicon carbide coarse particle, wherein the semi-insulating single-crystal silicon carbide coarse particle has a second silicon-vacancy concentration and a first particle diameter, the second silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}?3, and the first particle diameter is between 50 ?m and 350 ?m; self-impacting the semi-insulating single-crystal silicon carbide coarse particle to obtain a semi-insulating single-crystal silicon carbide powder, wherein the semi-insulating single-crystal sili
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: September 24, 2024
    Assignee: TAISIC MATERIALS CORP.
    Inventors: Dai-Liang Ma, Bang-Ying Yu, Bo-Cheng Lin
  • Patent number: 12100204
    Abstract: A method for image-guided agriculture includes receiving images; processing the images to generate reflectance maps respectively corresponding to spectral bands; synthesizing the reflectance maps to generate a multispectral image including vegetation index information of a target area; receiving crop information in regions of the target area; and assessing crop conditions for the regions based on the identified crop information and the vegetation index information.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: September 24, 2024
    Assignee: GEOSAT Aerospace & Technology Inc.
    Inventors: Cheng-Fang Lo, Kuang-Yu Chen, Te-Che Lin, Hsiu-Hsien Wen, Ting-Jung Chang