Abstract: A cushion for a wearable device includes an outer cover layer and an inner cushion. The outer cover layer includes a first base material, a heat conducting material and a first heat storage material. The heat conducting material and the first heat storage material are dispersed in the first base material. The enthalpy value of the outer cover layer is less than or equal to 5 J/g. The inner cushion includes a second base material and a second heat storage material. The second heat storage material is dispersed in the second base material. The enthalpy value of the inner cushion is greater than that of the outer cover layer. The difference between the enthalpy value of the inner cushion and the enthalpy value of the outer cover layer is greater than 45 J/g.

Abstract: A display substrate, a manufacturing method therefor, and a display device. The display substrate includes: a base substrate; a light-emitting substrate disposed on the base substrate and the light-emitting substrate being configured to emit incident light; a color conversion layer disposed at a side of the light emitting substrate away from the base substrate and the color conversion layer being configured to convert the incident light emitted from the light emitting substrate into light of a specific color; a selective reflection layer disposed on a side of the color conversion layer away from the base substrate and the selective reflection layer being configured to reflect incident light not converted by the color conversion layer to the color conversion layer and to transmit light of the specific color converted by the color conversion layer.

Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.

Abstract: Provided are a transformer winding and a method for constructing a transformer winding. The transformer winding includes: a lead wire of a winding conductor of the transformer winding; an insulating layer wrapping the lead wire; a ground shielding layer covering a side, close to the winding conductor, of the insulating layer; and a stress grading material layer, which is made of a semi-conductive material, covers a side, away from the winding conductor, of the insulating layer, and is electrically connected to the ground shielding layer, where the stress grading material layer is impedance-matched with the insulating layer.

Abstract: A package structure includes a first bonding film on a first package component and a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. In this case, an interference pattern can be formed by the optical signal passing through the varying spacing between the gratings of top wafer and bottom wafer due to pitch difference between first pitch and second pitch. By reading the optical signal, the resolution of overlay (misalignment) measurement is improved.

Abstract: A method includes forming a protruding fin, and forming a first dielectric layer including a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer includes a first top portion on a top surface of the protruding fin, and a sidewall portion on a sidewall of the protruding fin. The second dielectric layer is over the first top portion and the top surface of the protruding fin, and is formed using an anisotropic deposition process. The method further includes forming a dummy gate electrode on the second dielectric layer, forming a gate spacer on a sidewall of the dummy gate electrode, removing the dummy gate electrode, and forming a replacement gate electrode in a space left by the dummy gate electrode.

Abstract: An examining method for a coating layer on a wafer is provided, including providing an incident light to the coating layer and generating a reflecting light after the coating layer receives the incident light. A spectral analysis of the reflecting light is then generated and compared with a first reference waveform to determine a material of the coating layer. Moreover, the spectral analysis may be further compared with a second reference waveform to determine a thickness of the coating layer. The incident light and reflecting light are provided and received by a spectroscope which is placed above on the wafer to provide perpendicular optical paths to the coating layer on the upper surface of the wafer. By employing the disclosed method, the material and thickness of the coating layer on the wafer can be examined and further classified so as to enhance the conventional efficiency in the prior arts.

Abstract: The present disclosure provides an electrochemical measuring method. The method includes: providing a biochemical test chip including: an insulating substrate; an electrode unit, located on the insulating substrate and including a working electrode and a counter electrode; a first insulating septum, located on the electrode unit and having an opening at least partially exposing the electrode unit; a reactive layer, located at the opening and electrically connected to the electrode unit; and a second insulating septum, located on the first insulating septum, and reacting the reactive layer with a target analyte as a primary reaction. During the primary reaction, the counter electrode undergoes a self-redox reaction without interfering with the primary reaction, the self-redox reaction allows the counter electrode capable of receiving or releasing additional electrons, and a current density of the counter electrode is greater than a current density of the working electrode.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: Described herein are systems and methods that take advantage of a self-servicing mortgage engine that utilizes a language-model-based virtual assistant with access to knowledge databases, loan product databases, and underwriting databases. The mortgage engine integrates rules-based responses with the language model to analyze user input from conversations and provide context-aware interactive guidance, e.g., in the form of easy-to-understand explanations, instructions, and suggestions tailored to user questions. The interactive guidance generates recommendations and actionable outputs for borrowers that reduce the complexities of the lending process and drives the loan application. Advantageously, this increase efficiency and transparency for the borrower, while simultaneously reducing costs to lenders.

Abstract: Provided are a transformer winding and a method for constructing a transformer winding. The transformer winding includes: a winding conductor having a ring structure; a first insulating layer wrapped on a surface of the winding conductor formed by winding; a conductor tape attached in an unclosed surrounding manner to a surface of the first insulating layer along a circumferential direction of the first insulating layer, where the conductor tape is attached to a position having a minimum value of a leakage flux on the surface of the first insulating layer; a first shielding layer attached to the surface of the first insulating layer with the conductor tape attached thereto; a second insulating layer cast outside the first shielding layer; and a second shielding layer wrapped on an outer surface of the second insulating layer.

Abstract: A power adapter includes a flyback converter and a buck converter. If a first device is a preferred device, then power is allocated to the first device up to a first value. If a second device is plugged in, then power is re-allocating to the first device up to a second value and up to a third value to the second device. A total of the second value and the third value is up to the first value.

Abstract: Described herein are systems and methods that take advantage of a self-servicing mortgage engine that utilizes a language-model-based virtual assistant with access to knowledge databases, loan product databases, and underwriting databases. The mortgage engine integrates rules-based responses with the language model to analyze user input from conversations and provide context-aware interactive guidance, e.g., in the form of easy-to-understand explanations, instructions, and suggestions tailored to user questions. The interactive guidance generates recommendations and actionable outputs for borrowers that reduce the complexities of the lending process and drives the loan application. Advantageously, this increase efficiency and transparency to the borrower, while simultaneously reducing costs to lenders.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: Provided are a display panel and a display device. The display panel includes: a base substrate, including a plurality of light-emitting regions and a non-light-emitting region located between adjacent light-emitting regions; a pixel-defining layer, located on the base substrate and having a main body part and a plurality of openings defined by the main body part, each of the plurality openings being configured to define at least one of the plurality of light-emitting regions; a first structural layer at least located in one light-emitting region; a second structural layer at least located in the non-light-emitting region; the first structural layer has a first refractive index, the second structural layer has a second refractive index, and the first refractive index is greater than the second refractive index.