Abstract: A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell includes a control terminal, a data terminal and a source terminal. The first memory cell includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to the source terminal of the second memory cell for receiving a second source voltage.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: An interconnect for an electrochemical stack includes at least one of alternating air channel ribs of different length, seal gutters recessed relative to a perimeter seal surface on a fuel side of the interconnect, or fuel inlet and outlet plenums which extend perpendicular to fuel channels.

Abstract: An ultra-high-speed fully automatic precision spectral analysis system for rare earth metals and its working method is disclosed. The system includes a central control server, a precision numerical control rotary table communicatively connected with the central control server, a sample loading-clamping device, an automatic weighing device, an automatic ranging device, an analyzing surface machining device, a rare-earth spark emission spectrometer, and an automatic marking device; the sample loading-clamping device is arranged to fix a test sample of a rare earth metal, the automatic weighing device is arranged to weigh the test sample in real time, and the automatic ranging device, the analyzing surface machining device, the rare-earth spark emission spectrometer, and the automatic marking device are set up around the precision numerical control rotary table to perform the corresponding work processes respectively.

Abstract: The present disclosure relates to a content input method and apparatus for instant messaging software, and a device and a medium. The instant messaging software includes a first input box and a second input box, wherein the first input box and the second input box are switched by means of a switching control, and the sizes of the first t input box and the second input box are different. The method comprises: receiving target input content, which is input into a first input box, and displaying the target input content in the first input box; and in response to the triggering of a switching control, displaying the target input content in a second input box.

Abstract: Described herein are systems and methods for training machine learning models to generate three-dimensional (3D) motions based on light detection and ranging (LiDAR) point clouds. In various embodiments, a computing system can encode a machine learning model representing an object in a scene. The computing system can train the machine learning model using a dataset comprising synchronous LiDAR point clouds captured by monocular LiDAR sensors and ground-truth three-dimensional motions obtained from IMU devices. The machine learning model can be configured to generate a three-dimensional motion of the object based on an input of a plurality of point cloud frames captured by a monocular LiDAR sensor.

Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: Disclosed is a water flow switching device for sprinkler applications, the features of which include a projecting swing arm having a driven end, an oscillating end, and a supporting flange. The driven end extends to the exterior of an end wall and corresponding to a spray angle control mechanism to form a driven relationship. The oscillating end being located in a gear chamber. The supporting flange is mounted on a pivot seat. The oscillating end includes a first and a second oscillating position. A water shut-off device is disposed in the gear chamber. One side of the device has a first flap end, a second flap end, and a snap-over portion.

Abstract: A semiconductor package includes a carrier plate, a photonic integrated circuit chip, an electronic integrated circuit chip and an interposer substrate. The carrier plate has a notch and a first surface and a second surfaces opposite to the first surface, and the notch extends from the first surface toward the second surface. The photonic integrated circuit chip is disposed within the notch. The electronic integrated circuit chip is disposed on the first surface of the carrier plate. The photonic integrated circuit chip and the electronic integrated circuit chip are disposed on the carrier through the interposer substrate.

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

Abstract: Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

Abstract: The invention provides a carbon dioxide-based polyurethane elastomer with damping and anti-fatigue aging properties and its preparation method. It is obtained from Component A and Component B; Component A includes: PTMG-1000 45˜60 parts, carbon dioxide-based polyol 25˜30 parts, poly-DOPO-ITA-pentanediol ester 10˜20 parts, BDO 3˜5 parts, water 0.3˜0.5 parts, N-methylimidazole 0.5˜0.8 parts, bis(2-dimethylaminoethyl) ether 0.1˜0.2 parts, needle-shaped nano-titanium dioxide 0.5 parts, hindered phenol 0.2˜0.5 parts, dibutyltin dilaurate 0.1˜0.3 parts, strontium chloride 0.005˜0.01 parts, rhodium chloride 0.02˜0.03 parts, foaming agent 0.2˜0.5 parts; Component B includes: carbon dioxide-based polyol 50˜55 parts, MDI-50 45˜50 parts, organic zinc 0.01˜0.02 parts, organic bismuth 0.01˜0.02 parts.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: A plurality of holes in a top surface of a silicon medium form a plurality of sub-meta lenses to result in multiple focal points rather than a single point (resulting from using a single meta lens). As a result, optical paths for incoming light are reduced as compared with a single optical path associated with a single meta lens, which in turn reduces angular response of incident photons. Thus, a pixel sensor including the plurality of sub-meta lenses experiences improved light focus and greater signal-to-noise ratio. Additionally, dimensions of the pixel sensor are reduced (particularly a height of the pixel sensor), which allows for greater miniaturization of an image sensor that includes the pixel sensor.

Abstract: An image sensor includes a semiconductor substrate, a first isolation structure, a visible light detection structure, and an infrared light detection structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface in a vertical direction. The first isolation structure is disposed in the semiconductor substrate for defining pixel regions in the semiconductor substrate. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region, and a first portion of the visible light detection structure is disposed between the second surface of the semiconductor substrate and the infrared light detection structure in the vertical direction. The infrared light detection structure includes an epitaxial structure disposed in the semiconductor substrate, and the visible light detection structure includes a doped region including a material identical to a material of the semiconductor substrate.