Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes channel layers, a mask structure, a gate structure and a source/drain pattern. The channel layers are stacked vertically apart along a first direction over a substrate. The mask structure is disposed over and apart from the channel layers along the first direction. The gate structure laterally extends along a second direction perpendicular to the first direction disposed, wherein the gate structure wraps around the channel layers and laterally surround the mask structure. The source/drain pattern is in contact with the channel layers.

Abstract: A chain lock comprises a lock body with a cylindrical shape and a chain connected to the lock body at one end and to a bolt at the other end. The lock body has two shells, with the second shell sleeved within the first shell. Inside the second shell, there is a lock core, a lock seat, and an installation seat. The lock seat and the chain are connected at opposite ends of the installation seat. An actuating element connects the lock core and the lock seat, allowing them to rotate simultaneously. The side wall of the lock seat features an insertion portion for inserting the bolt comprising a first slot and a second slot, wherein the width of the first slot is greater than the width of the second slot.

Abstract: Disclosed are methods, devices and the non-transitory computer storage media of matching clinical trials. The present disclosure provides a method of matching clinical trials. The method comprises: obtaining a first data set from a pathology report; obtaining a second data set of a clinical trial; determining whether the first data set and the second data set are matched with respect to a first set of fields; determining a relevance value between the first data set and the second data set with respect to a second set of fields when the first data set and the second data set are matched with respect to the first set of fields; and determining the clinical trial as recommended when the relevance value exceeds a threshold.

Abstract: Disclosed are a device and a method for transferring the semiconductor component, which aims to accurately measure the movement accuracy of a transfer stamp when transferring semiconductor components using a transfer stamp, thereby improving the alignment accuracy between the transfer stamp and the semiconductor component, ensuring the yield rate of the prepared products, and solving the problem in the related art that after the transfer stamp is aligned with a temporary carrier or a drive circuit backplane, the semiconductor components cannot be guaranteed by only relying on the large stroke up and down movement of the guide rail. The precise picking up of LED chips or accurate placement of them at the predetermined position on the driver circuit backplane results in a decrease in the transfer yield, affecting the technical issues of subsequent related processes.

Abstract: A method includes following steps. A dielectric layer is formed over a substrate. A transition metal-containing layer is deposited on the dielectric layer. The transition metal-containing layer is patterned into a plurality of transition metal-containing pieces. The transition metal-containing pieces are sulfurized or selenized to form a plurality of semiconductor seeds. Semiconductor films are grown from semiconductor seeds. Transistors are formed on the semiconductor films.

Abstract: Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial semiconductor structures (e.g., fins) are formed with metal gate structures in a through via region. An opening is formed through BEOL layers to expose the metal gates, which may then be removed. A liner layer is formed on sidewalls of the opening including on semiconductor structures extending from the substrate. The opening is then extended into the substrate and a through substrate via is formed from the extended opening.

Abstract: An image sensor includes a first color filter disposed on a first photodiode, a first grid, and a first micro lens disposed on the first color filter and the first grid. The first grid includes a first main portion and a first shielding portion extended from the first main portion. The first main portion surrounds the first color filter and the first shielding portion partially covers the first color filter such that a first cavity defined by the first shielding portion is configured over the first color filter. The first color filter or the first micro lens includes a first protruding portion filled in the first cavity, and a width of the first protruding portion is in a range from 0.1 pixel size to 0.8 pixel size. A manufacturing method of an image sensor is also disclosed.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: A display device includes a bezel, first and second light guide plates (LGP), first and second light emitting element, first and second reflection sheets, a first fixing member, and at least one display panel. Each of the first and second LGPs has a bottom surface, a light exit surface, a light incident surface, and a first side surface. The first and second reflection sheets are located between the bezel and the first LGP and between the bezel and the second LGP, respectively. Bent portions of the first and second reflection sheets are disposed beside the first side surface of the first LGP and the first side surface of the second LGP, respectively and located between the first side surface of the first LGP and the first side surface of the second LGP. The first fixing member is sandwiched between the bent portions of the first and second reflection sheets.

Abstract: A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a plurality of fins over a substrate, and forming dummy gates patterned over the fins. Each dummy gate has a spacer on sidewalls of the patterned dummy gates. The method also includes forming recesses in the fins by using the patterned dummy gates as a mask, forming a passivation layer over the fins and in the recesses in the fins, and patterning the passivation layer to leave a remaining passivation layer in some of the recesses in the fins.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work function layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work function layer fully fills spaces between the second channel nanostructures.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.