Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

Abstract: A new method to form color image sensor cells without damaging bonding pads in the manufacture of an integrated circuit device is achieved. The method comprises, first, forming cell electrodes and bonding pads on a semiconductor substrate. A passivation layer is formed overlying the cell electrodes but exposing the top surface of the bonding pads. The semiconductor substrate is then dipped in a hydrogen peroxide solution to thereby form a metal oxide layer overlying the bonding pads. A first transparent planarization layer is deposited overlying the passivation layer and the metal oxide layer. A color filter photoresist layer is deposited overlying the first transparent planarization layer. The color filter photoresist layer is patterned to form color filter elements to complete the color image sensor cells in the manufacture of the integrated circuit device. The presence of the metal oxide layer prevents damage to the bonding pads from an alkaline developer.

Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

Abstract: Within a method for fabricating a microelectronic, and a microelectronic fabrication fabricated in accord with the method, there is formed upon a bond pad formed over a substrate a conductor passivation layer. Within the method and the microelectronic fabrication, the bond pad is formed from a conductor material selected from the group consisting of aluminum and aluminum alloy conductor materials, and the conductor passivation layer is formed from a noble metal conductor material. The invention provides particular value for fabricating color filter sensor image array optoelectronic microelectronic fabrications with attenuated bond pad corrosion.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

Abstract: A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.

Abstract: A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A method for alignment to an alignment mark array within a patterned electronic material layer, formed on a substrate employed in a microelectronics fabrication, with improved registration accuracy of a subsequent step-and-repeat photomask pattern. There is first provided a substrate upon which is formed a patterned microelectronics layer containing an alignment mark array. There is then formed over the substrate and patterned layer, covering over the alignment marks, a subsequent layer or layers which may be of opaque material. In order to align properly a patterned photomask for patterning the overlying layer by means of conventional photolithography, the alignment mark array is located by first scanning with a laser light source contained within a step-and-repeat apparatus containing the patterned photomask and detecting the optical radiation signal scattered from the alignment mark array.

Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bump's. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.

Abstract: A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bumps. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.

Abstract: A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening.

Abstract: Within a method for fabricating an microelectronic fabrication there is first provided a substrate employed within an optoelectronic microelectronic fabrication, where the substrate comprises an optoelectronic microelectronic device which is in electrical communication with a bond pad formed over the substrate. There is then processed, when fabricating the substrate to form the optoelectronic microelectronic fabrication, the substrate in the absence of optoelectronically transducable radiation, in order to attenuate corrosion of the bond pad. The method is particularly useful for forming a color filter sensor image array optoelectronic microelectronic fabrication comprising multiple photoresist based patterned colored filter layers.

Abstract: A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 Å layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes.

Abstract: A metal code process for a read-only memory (ROM) combines the alignment dip back process (to reduce the polyoxide thickness over the gate electrode and to protect the field oxide) with a double charge implant approach to provide the function of a depletion mode ROM cell. The alignment dip back process also avoids leakage current problems. A stable depletion mode device character is achieved by implant step energies greater than 150 keV.