Abstract: An interconnect for an electrochemical stack includes at least one of alternating air channel ribs of different length, seal gutters recessed relative to a perimeter seal surface on a fuel side of the interconnect, or fuel inlet and outlet plenums which extend perpendicular to fuel channels.

Abstract: A double-layer cholesteric liquid crystal display and its manufacturing method are disclosed. The double-layer cholesteric liquid crystal display includes three transparent substrates, two opposing electrode layers, two cholesteric liquid crystal layers, and a first light-absorbing layer. Additionally, the double-layer cholesteric liquid crystal display incorporates two drive ICs and a second light-absorbing layer. The two drive ICs can be positioned either on the same side or on opposite sides within the non-display area of the double-layer cholesteric liquid crystal display. Furthermore, the first cholesteric liquid crystal layer exhibits a first color light, and the second cholesteric liquid crystal layer exhibits a second color light, where the colors are selected as contrasting colors. Additionally, the two cholesteric liquid crystal layers possess mutually opposite optical rotary properties.

Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions; forming first to fifth gate electrodes, the second gate electrode being between the first and third gate electrodes, the fourth gate electrode being between the third and fifth gate electrodes; and selectively replacing at least one portion of at least one of the gate electrodes with an isolation dummy gate, including: replacing the first and fifth gate electrodes with first and second isolation dummy gates formed in trenches through the first and second active regions; and replacing a first portion of the third gate electrode overlying the second active region with a third isolation dummy gate formed in a first trench through the second active region, resulting in a second portion of the third gate over the first active region, and the third isolation dummy gate aligned with the second portion of the third gate.

Abstract: A spliced reflective display includes multiple display devices, a front light guide plate, and at least one light source. Among the multiple display devices, one display device is joined side-by-side with another to form an adjacent joint. The front light guide plate is affixed above the multiple display devices and is close to the display side. It has a top surface near the display side and includes an optical structure. The at least one light source is positioned at the side of the front light guide plate, and light therefrom reflects off the top surface of the front light guide plate onto the multiple display devices, and the reflected light from the display devices forms image light that is directed towards the display side to produce an image. The optical structure directs the path of the image light to obscure the adjacent joint from being visible on the display side.

Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.

Abstract: A spliced reflective display includes multiple display devices, a front light guide plate, and at least one light source. Among the multiple display devices, one display device is joined side-by-side with another to form an adjacent joint. The front light guide plate is affixed above the multiple display devices and is close to the display side. It has a top surface near the display side and includes an optical structure. The at least one light source is positioned at the side of the front light guide plate, and light therefrom reflects off the top surface of the front light guide plate onto the multiple display devices, and the reflected light from the display devices forms image light that is directed towards the display side to produce an image. The optical structure directs the path of the image light to obscure the adjacent joint from being visible on the display side.

Abstract: A double-layer cholesteric liquid crystal display and its manufacturing method are disclosed. The double-layer cholesteric liquid crystal display includes three transparent substrates, two opposing electrode layers, two cholesteric liquid crystal layers, and a first light-absorbing layer. Additionally, the double-layer cholesteric liquid crystal display incorporates two drive ICs and a second light-absorbing layer. The two drive ICs can be positioned either on the same side or on opposite sides within the non-display area of the double-layer cholesteric liquid crystal display. Furthermore, the first cholesteric liquid crystal layer exhibits a first color light, and the second cholesteric liquid crystal layer exhibits a second color light, where the colors are selected as contrasting colors. Additionally, the two cholesteric liquid crystal layers possess mutually opposite optical rotary properties.

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

Abstract: A front light guide plate and a reflective display are provided. The reflective display includes a front light guide plate, a light source and a display device, and the front light guide plate includes a first surface and a second surface corresponding to the first surface. A first surface includes a plurality of optical structures. Each optical structure includes a first optical surface, and a second optical surface disposed with the first optical surface in face-to-face fashion. The light source is implemented on the side of the front light guide plate, and the display device is provided with a second surface. When the light beams from the light source are reflected by the first optical surface of the front light guide plate and enter the display device, portion of the light beams emitted from the first optical surface to the second optical surface will be absorbed or scattered by the light reducing layer.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.

Abstract: A fuel cell interconnect includes an air side and an opposing fuel side, air ribs disposed on the air side and at least partially defining air channels, and fuel ribs disposed on the fuel side and a least partially defining fuel channels. The fuel channels include central fuel channels disposed in a central fuel field, the central fuel channels having a cross-sectional area A1, peripheral fuel channels disposed in peripheral fuel fields that are disposed on opposing sides of the central fuel field, the peripheral fuel channels having a cross-sectional area A3, and intermediate fuel channels disposed in intermediate fuel fields that are disposed between the central fuel field and the peripheral fuel fields, the intermediate fuel channels having a cross-sectional area A2, where area A1<area A2<area A3.

Abstract: An electrochemical cell stack includes electrochemical cells that each contain a fuel electrode, an air electrode and an electrolyte disposed therebetween, interconnects disposed between the electrochemical cells, and an interconnect end plate disposed over the fuel electrode of an outermost one of the electrochemical cells. The interconnect end plate includes a fuel side, an opposing air side, fuel ribs disposed on the fuel side and at least partially defining fuel channels, air ribs disposed on the air side and at least partially defining dummy air channels, fuel holes extending from the fuel side to the air side, and recessed ring seal regions disposed on the air side surrounding the fuel holes.

Abstract: An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.

Abstract: A method of making an interconnect for an electrochemical cell stack includes providing the interconnect, and creep flattening the interconnect prior to placing the interconnect into the electrochemical cell stack.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.

Abstract: A method of making an interconnect for an electrochemical cell stack includes providing the interconnect, and creep flattening the interconnect prior to placing the interconnect into the electrochemical cell stack.

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

Abstract: A cross-flow interconnect and a fuel cell stack including the same, the interconnect including fuel inlets and outlets that extend through the interconnect adjacent to opposing first and second peripheral edges of the interconnect; an air side; and an opposing fuel side. The air side includes an air flow field including air channels that extend in a first direction, from a third peripheral edge of the interconnect to an opposing fourth peripheral edge of the interconnect; and riser seal surfaces disposed on two opposing sides of the air flow field and in which the fuel inlets and outlets are formed. The fuel side includes a fuel flow field including fuel channels that extend in a second direction substantially perpendicular to the first direction, between the fuel inlets and outlets; and a perimeter seal surface surrounding the fuel flow field and the fuel inlets and outlets.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.