Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.

Abstract: A method of forming a fuel cell interconnect includes depositing a Cr alloy powder, sintering the Cr alloy powder, and repeating the depositing and the sintering to form the fuel cell interconnect. The Cr alloy powder may include a pre-alloyed powder containing from about 4 wt. % to about 6 wt. % Fe, and from about 94 wt. % to about 96 wt. % Cr.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A cross-flow interconnect and a fuel cell stack including the same, the interconnect including fuel inlets and outlets that extend through the interconnect adjacent to opposing first and second peripheral edges of the interconnect; an air side; and an opposing fuel side. The air side includes an air flow field including air channels that extend in a first direction, from a third peripheral edge of the interconnect to an opposing fourth peripheral edge of the interconnect; and riser seal surfaces disposed on two opposing sides of the air flow field and in which the fuel inlets and outlets are formed. The fuel side includes a fuel flow field including fuel channels that extend in a second direction substantially perpendicular to the first direction, between the fuel inlets and outlets; and a perimeter seal surface surrounding the fuel flow field and the fuel inlets and outlets.

Abstract: An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

Abstract: A method of making an interconnect for an electrochemical cell stack includes providing the interconnect, and creep flattening the interconnect prior to placing the interconnect into the electrochemical cell stack.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: A semiconductor device, method, and system of arranging patterns of the same are provided. The method includes generating a plurality of gate patterns and conductive patterns, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Abstract: Various embodiments include fuel cell interconnects having a fuel distribution portion having an inlet opening, a fuel collection portion having an outlet opening, and a primary fuel flow field containing channels, wherein the fuel distribution portion comprises at least one raised feature defining a fuel distribution flow path, and the fuel distribution flow path is not continuous with the channels in the primary fuel flow field. The at least one raised feature may include, for example, a network of ribs and/or dots. Further embodiments include interconnects having a fuel distribution portion with a variable surface depth to provide variable flow restriction and/or a plenum with variable surface depth and raised a raised relief feature on the cathode side, and/or varying flow channel depths and/or rib heights adjacent a fuel hole.

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Abstract: A method of making an interconnect for a solid oxide fuel cell stack includes contacting an interconnect powder located in a die cavity with iron, the interconnect powder including a chromium and iron, compressing the interconnect powder to form an interconnect having ribs and fuel channels on a first side of the interconnect, such that the iron is disposed on tips of the ribs; and sintering the interconnect, such that the iron forms an contact layer on the tips of the ribs having a higher iron concentration than a remainder of the interconnect. A glass containing cathode contact layer having a glass transition temperature of 900° C. or less may be located over the rib tips on the oxidant side of the interconnect.

Abstract: A cross-flow interconnect and a fuel cell stack including the same, the interconnect including fuel inlets and outlets that extend through the interconnect adjacent to opposing first and second peripheral edges of the interconnect; an air side; and an opposing fuel side. The air side includes an air flow field including air channels that extend in a first direction, from a third peripheral edge of the interconnect to an opposing fourth peripheral edge of the interconnect; and riser seal surfaces disposed on two opposing sides of the air flow field and in which the fuel inlets and outlets are formed. The fuel side includes a fuel flow field including fuel channels that extend in a second direction substantially perpendicular to the first direction, between the fuel inlets and outlets; and a perimeter seal surface surrounding the fuel flow field and the fuel inlets and outlets.

Abstract: A cross-flow interconnect and a fuel cell stack including the same, the interconnect including fuel inlets and outlets that extend through the interconnect adjacent to opposing first and second peripheral edges of the interconnect; an air side; and an opposing fuel side. The air side includes an air flow field including air channels that extend in a first direction, from a third peripheral edge of the interconnect to an opposing fourth peripheral edge of the interconnect; and riser seal surfaces disposed on two opposing sides of the air flow field and in which the fuel inlets and outlets are formed. The fuel side includes a fuel flow field including fuel channels that extend in a second direction substantially perpendicular to the first direction, between the fuel inlets and outlets; and a perimeter seal surface surrounding the fuel flow field and the fuel inlets and outlets.

Abstract: A method of making an interconnect for a solid oxide fuel cell stack includes providing an iron rich material containing at least 25 wt. % iron into channels of a mold, providing a powder containing 4-6 wt. % Fe, 0-1 wt. % Y and balance Cr into the mold over the iron rich material containing at least 25 wt. % iron, compacting the iron rich material containing at least 25 wt. % iron and the powder comprising 4-6 wt. % Fe, 0-1 wt. % Y and balance Cr in the mold to form the interconnect, and sintering the interconnect to form a sintered interconnect having iron rich regions having an iron concentration greater than 10% in ribs of the interconnect.