Abstract: Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.

Abstract: A semiconductor structure can include a first substrate having a frontside and a backside opposite the frontside. The semiconductor structure can include devices on the frontside. The semiconductor structure can include first interconnect structures on the frontside and coupled to the devices. The semiconductor structure can include a heat distribution layer on the frontside and electrically isolated from the first interconnect structures, where the heat distribution layer includes a thermally conductive material. The semiconductor structure can include a second substrate coupled to the first substrate on the frontside. The semiconductor structure can include second interconnect structures on the backside and coupled to the devices.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Abstract: An image interpolation method comprises applying a filter to an RGBIR image to generate a LUMA image; calculating two gradients according to the LUMA image; and interpolating a missing pixel between two pixels in the RGBIR image according to the two gradients. Wherein each gradient corresponding to two LUMA pixels in the LUMA image. An image fusion method comprises applying a filter to an RGBIR image to generate a LUMA image; obtaining an R-image, a G-image, a B-image and an IR image according to the RGBIR image; and generating a fusion image according to the R-image, G-image, B-image, the IR image and the LUMA image.

Abstract: A multilayer polymer capacitor (MLPC), including a casing, a multilayer core, an electroplated positive terminal, a first electroplated negative terminal, and a second electroplated negative terminal. The casing includes a casing body and a cover plate. The casing body is provided with an accommodating cavity, whose bottom is provided with a through hole. The multilayer core is provided in the accommodating cavity. An anode lead-out part and a cathode lead-out part are provided at two ends of the accommodating cavity, respectively. The electroplated positive terminal and the first electroplated negative terminal are provided on outer side surfaces of two ends of the casing, respectively. The second electroplated negative terminal is provided on an outer bottom surface of the casing, and is electrically connected to the multilayer core.

Abstract: A detection system for a vehicle comprises a blind spot detection module and a glasses module. The blind spot detection module comprises a first video recording device recording a vehicle surrounding image; a first identification device generating a blind spot identification result; a first determination device determining whether to transmit the vehicle surrounding image and/or a blind spot warning message; and a transmitting device transmitting the vehicle surrounding image and/or the blind spot warning message.

Abstract: An electronic system is provided, which includes a host device and a display device. The host device includes a first signal conversion circuit and a first signal transmission circuit. The first signal conversion circuit is utilized for converting signals associated with the host device into a first universal serial bus signal. The display device includes a display panel, a second signal conversion circuit and a second signal transmission circuit. The second signal transmission circuit is utilized for receiving the first universal serial bus signal. The second signal conversion circuit is coupled to the second signal transmission circuit for converting the first universal serial bus signal into the signals associated with the host device. The first universal serial bus signal conforms to universal serial bus 4.0 or above version standard specification.

Abstract: A detection system for a vehicle comprises a blind spot detection module and a glasses module. The blind spot detection module comprises a first video recording device recording a vehicle surrounding image; a first identification device generating a blind spot identification result; a first determination device determining whether to transmit the vehicle surrounding image and/or a blind spot warning message; and a transmitting device transmitting the vehicle surrounding image and/or the blind spot warning message.

Abstract: In semiconductor manufacturing, deionized (DI) water or another process fluid is flowed through a nonmetallic pipe and onto a semiconductor wafer. Static electric charge is discharged from the DI water or other process fluid flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded. The nonmetallic pipe may comprise fluoropolymer (PFA) based tubing. In some embodiments, the nonmetallic pipe includes: a PFA-NE pipe connected with a chamber or housing containing the wafer, and a second pipe connected with the PFA-NE pipe by a pipe connector, in which the second pipe is more electrically insulating than the PFA-NE pipe.

Abstract: An electronic system is provided, which includes a host device and a display device. The host device includes a first signal conversion circuit and a first signal transmission circuit. The first signal conversion circuit is utilized for converting signals associated with the host device into a first universal serial bus signal. The display device includes a display panel, a second signal conversion circuit and a second signal transmission circuit. The second signal transmission circuit is utilized for receiving the first universal serial bus signal. The second signal conversion circuit is coupled to the second signal transmission circuit for converting the first universal serial bus signal into the signals associated with the host device. The first universal serial bus signal conforms to universal serial bus 4.

Abstract: A circuit used in a network device, which includes a memory and an analyzer. The memory stores an ACL look-up table, wherein the ACL look-up table includes multiple ACL rules, and each ACL rule contains at least a comparison field, a control field, and a logical operation field. The comparison field includes comparison information of a communication protocol, the control field indicates whether said each ACL rule needs to be combined with a next ACL rule, and the logic operation field indicates a logical operation used when said each ACL rule needs to be combined with the next ACL rule. The analyzer is configured to sequentially compare the packet according to multiple ACL rules recorded in the ACL look-up table, so as to generate at least one comparison result for determining the processing method of the packet.