Patents by Inventor Chenming Hu

Chenming Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual work function CMOS gate technology based on metal interdiffusion
    Patent number: 7141858
    Abstract: A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: November 28, 2006
    Assignee: The Regents of the University of California
    Inventors: Igor Polishchuk, Pushkar Ranade, Tsu-Jae King, Chenming Hu
  • Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
    Publication number: 20060261490
    Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
    Type: Application
    Filed: July 28, 2006
    Publication date: November 23, 2006
    Inventors: Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Chender Huang, Shang Hou, Shin Jeng, Hao-Yi Tsai, Chenming Hu
  • Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
    Publication number: 20060255365
    Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 16, 2006
    Inventors: Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu
  • Contacts to semiconductor fin devices
    Publication number: 20060244066
    Abstract: A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.
    Type: Application
    Filed: June 30, 2006
    Publication date: November 2, 2006
    Inventors: Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
  • Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
    Patent number: 7126225
    Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 24, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Chender Huang, Shang Y. Hou, Shin Puu Jeng, Hao-Yi Tsai, Chenming Hu
  • Self-aligned contact for silicon-on-insulator devices
    Publication number: 20060234438
    Abstract: A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
    Type: Application
    Filed: June 16, 2006
    Publication date: October 19, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Liang Yang, Yee-Chia Yeo, Horng-Huei Tseng, Chenming Hu
  • Doping of semiconductor fin devices
    Publication number: 20060234431
    Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
    Type: Application
    Filed: June 5, 2006
    Publication date: October 19, 2006
    Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Method of fabricating a necked FINFET device
    Patent number: 7122412
    Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haur-Ywh Chen, Fang-Cheng Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang, Chenming Hu
  • Resistor with reduced leakage
    Publication number: 20060226487
    Abstract: A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
    Type: Application
    Filed: June 12, 2006
    Publication date: October 12, 2006
    Inventors: Yee-Chia Yeo, Chenming Hu
  • HYBRID FRACTIONAL-BIT SYSTEMS
    Publication number: 20060227021
    Abstract: The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 12, 2006
    Inventors: Chenming HU, Guobiao ZHANG
  • Doping of semiconductor fin devices
    Publication number: 20060220133
    Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
    Type: Application
    Filed: June 5, 2006
    Publication date: October 5, 2006
    Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Method for forming a device having multiple silicide types
    Patent number: 7112483
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
    Patent number: 7112495
    Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu
  • High performance tunneling-biased MOSFET and a process for its manufacture
    Publication number: 20060208316
    Abstract: A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.
    Type: Application
    Filed: March 16, 2005
    Publication date: September 21, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Yi-Ling Chang, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Semiconductor structure having a strained region and a method of fabricating same
    Publication number: 20060208336
    Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.
    Type: Application
    Filed: April 21, 2006
    Publication date: September 21, 2006
    Inventors: Wen-Chin Lee, Chung-Hu Ke, Chenming Hu
  • Copper wiring with high temperature superconductor (HTS) layer
    Patent number: 7105928
    Abstract: Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Horng-Huei Tseng, Chenming Hu, Chao-Hsiung Wang
  • Contacts to semiconductor fin devices
    Patent number: 7105894
    Abstract: A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
  • Strained channel complementary field-effect transistors and methods of manufacture
    Patent number: 7101742
    Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: September 5, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chenming Hu
  • Thermal anneal process for strained-Si devices
    Patent number: 7098119
    Abstract: A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: August 29, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chung-Hu Ke, Wen-Chin Lee, Chenming Hu
  • Strained channel complementary field-effect transistors and methods of manufacture
    Publication number: 20060189056
    Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.
    Type: Application
    Filed: April 20, 2006
    Publication date: August 24, 2006
    Inventors: Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chenming Hu