Patents by Inventor Chenming Hu

Chenming Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060177997
    Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.
    Type: Application
    Filed: March 16, 2006
    Publication date: August 10, 2006
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu, Shang-Chih Chen, Chih-Hao Wang, Fu-Liang Yang, Yee-Chia Yeo
  • Publication number: 20060170053
    Abstract: A transistor (1) having, a fin (2) and a gate electrode (3) extending on more than one side of the fin (2) to comprise more than one gate (9) of the transistor (1), and a dopant in each of a source (6), drain (7) and a channel region (8), comprising a single dopant type.
    Type: Application
    Filed: May 9, 2003
    Publication date: August 3, 2006
    Inventors: Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
  • Patent number: 7081395
    Abstract: A method of forming a strained silicon layer created via a material mis-match with adjacent trench isolation (TI), regions filled with a dielectric layer comprised with either a higher, or lower thermal expansion coefficient than that of silicon, has been developed. Filling of trenches with a dielectric layer comprised with a higher thermal expansion coefficient than that of silicon results in a tensile strain in planar direction and compressive strain in vertical direction, in an adjacent silicon region. Enhanced electron mobility in channel regions of an N channel MOSFET device, and enhanced hole mobility and transit time in an N type base region of a vertical PNP bipolar device, is realized when these elements are formed in the silicon layer under tensile strain.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: July 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Hwa Chi, Yee-Chia Yeo, Chenming Hu
  • Publication number: 20060159423
    Abstract: To protect copyright, the present invention provides a tamper-proof content-playback system. Its content-playback unit has the following I/O characteristics: A) at least a portion of its content input(s) is encrypted digital signals; B) at least a portion of its content output(s) is non-digital (e.g. analog) or non-electrical (e.g. image) signals. Only secure data connections are allowed for decrypted contents inside the content-playback unit. Accordingly, its components are preferably integrated into: a single chip, a single package, or a chip/package-on-panel.
    Type: Application
    Filed: February 25, 2005
    Publication date: July 20, 2006
    Inventors: Guobiao ZHANG, Chenming HU
  • Publication number: 20060159424
    Abstract: To protect copyright, the present invention provides a tamper-proof content-playback system. Its content-playback unit has the following I/O characteristics: A) at least a portion of its content input(s) is encrypted digital signals; B) at least a portion of its content output(s) is non-digital (e.g. analog) or non-electrical (e.g. image) signals. Only secure data connections are allowed for decrypted contents inside the content-playback unit. Accordingly, its components are preferably integrated into: a single chip, a single package, or a chip/package-on-panel.
    Type: Application
    Filed: February 25, 2005
    Publication date: July 20, 2006
    Inventors: Chenming HU, Guobiao ZHANG
  • Publication number: 20060158737
    Abstract: To protect copyright, the present invention provides a tamper-proof content-playback system. Its content-playback unit has the following I/O characteristics: A) at least a portion of its content input(s) is encrypted digital signals; B) at least a portion of its content output(s) is non-digital (e.g. analog) or non-electrical (e.g. image) signals. Only secure data connections are allowed for decrypted contents inside the content-playback unit. Accordingly, its components are preferably integrated into: a single chip, a single package, or a chip/package-on-panel.
    Type: Application
    Filed: February 25, 2005
    Publication date: July 20, 2006
    Inventors: Chenming HU, Guobiao ZHANG
  • Patent number: 7074656
    Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: July 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Patent number: 7071052
    Abstract: A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: July 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Publication number: 20060138557
    Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
    Type: Application
    Filed: February 17, 2006
    Publication date: June 29, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Chao-Hsing Wang, Chung-Hu Ge, Chenming Hu
  • Publication number: 20060124965
    Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 15, 2006
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Patent number: 7057237
    Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: June 6, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Howard Chih Hao Wang, Chenming Hu, Chun-Chieh Lin
  • Publication number: 20060113591
    Abstract: An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 1, 2006
    Inventors: Chih-Hao Wan, Ta-Wei Wang, Chenming Hu
  • Patent number: 7052964
    Abstract: A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: May 30, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee, Chenming Hu
  • Patent number: 7045836
    Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: May 16, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chin Lee, Chung-Hu Ge, Chenming Hu
  • Patent number: 7045847
    Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: May 16, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu, Shang-Chih Chen, Chih-Hao Wang, Fu-Liaog Yang, Ye-Chia Yeng
  • Patent number: 7037772
    Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 2, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Publication number: 20060084211
    Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.
    Type: Application
    Filed: October 19, 2004
    Publication date: April 20, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Yi-Lang Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu
  • Publication number: 20060081875
    Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.
    Type: Application
    Filed: October 18, 2004
    Publication date: April 20, 2006
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chenming Hu
  • Patent number: 7029994
    Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hu Ge, Chao-Hsiung Wang, Chien-Chao Huang, Wen-Chin Lee, Chenming Hu
  • Patent number: 7022561
    Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: April 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Chao-Hsing Wang, Chung-Hu Ge, Chenming Hu