Patents by Inventor Chenxiao Ren

Chenxiao Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Frequency synthesizers with dynamic calibration intervals
    Patent number: 8552804
    Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 8, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Chenxiao Ren, Tao Jing
  • Method and apparatus for analog smooth switch in VCO loading control
    Patent number: 7834708
    Abstract: A method and apparatus for analog smooth switch in VCO loading control, in one technique, receiving an input signal to adjust a frequency of an oscillator; activating one or more switches to control a current source/sink based on the received input signal; applying the current source/sink to a capacitor to adjust a voltage on the capacitor; and applying the voltage on the capacitor to one or more switches, each of the one or more switches connected between a load and a stage of the oscillator.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: November 16, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chenxiao Ren
  • Clock generator with self-bias bandwidth control
    Patent number: 7586347
    Abstract: A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generates a charge current based on the bias voltage. The charge pump generates an output based on the charge current to maintain a constant open-loop bandwidth of the phase-lock loop.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: September 8, 2009
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chenxiao Ren, Zhongyuan Chang