Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.

Abstract: A clamp assembly includes at least one clamp which is provided to clamp a workpiece in electroless plating, etching, electroplating or cleaning process. The clamp includes a base, a clamping element and a limiting element. The base is mounted on a carrier and includes a guide hole and a first limiting hole which are communicated with each other. The clamping element includes a guide rod and a second limiting hole, the guide rod is inserted into the guide hole to allow the second limiting hole located on the guide hole to be communicated with the first limiting hole. The limiting element is inserted into the first and second limiting holes to integrate the base with the clamping element for clamping the workpiece.

Abstract: An inverter circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, a tunable pull-up circuit, a tunable pull-down circuit, and a control circuit. The first MOS transistor has a control terminal configured to receive a first input signal, a first connection terminal, and a second connection terminal. The second MOS transistor has a control terminal configured to receive the first input signal, a first connection terminal, and a second connection terminal coupled to the second control terminal of the first MOS transistor. The tunable pull-up circuit is coupled between the first connection terminal of the first MOS transistor and a first reference voltage. The tunable pull-down circuit is coupled between the first connection terminal of the second MOS transistor and a second reference voltage. The control circuit adaptively adjusts pull-up strength of the tunable pull-up circuit and pull-down strength of the tunable pull-down circuit.

Abstract: The present disclosure discloses a package including a first support portion, a second support portion, and multiple pins. The first support portion includes a first upper metal layer and a first lower metal layer, wherein the first lower metal layer is connected to and overlaps with the first upper metal layer, corresponding to the position of the first upper metal layer. The second support portion is laterally separated from the first support portion, and the second support portion includes a second metal layer. The multiple pins are laterally separated from the first support portion and the second support portion, where in a top view, a ratio of a maximum length of the second metal layer to a maximum length of the package is greater than ?.

Abstract: A package structure is provided herein, which includes a substrate, an integrated transistor, and an encapsulation structure. The integrated transistor is disposed on the substrate and includes a transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The transistor includes a gate, a drain, and a source. The capacitor is electrically connected to the gate, and the resistor is electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The encapsulation structure encapsulates the integrated transistor. The package structure includes a gate terminal, a drain terminal, and a source terminal.

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

Abstract: A calibration circuit of a pulse-frequency modulation (PFM) converter includes a signal generator circuit and a calibration control circuit. The signal generator circuit generates and outputs an emulated slope signal to a comparator circuit under a calibration mode, wherein the emulated slope signal has an emulated slope following an initial voltage, and the emulated slope corresponds to a slope of a sensed signal indicative of electrical characteristic of an inductor of the PFM converter. The calibration control circuit refers to an output signal that is generated from a PFM control circuit in response to an output signal of the comparator circuit, to calibrate at least one circuit of the PFM converter.

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

Abstract: A styrene-isoprene/butadiene diblock copolymer contains a polystyrene block and a polyisoprene/butadiene block. Based on 100 wt % of the styrene-isoprene/butadiene diblock copolymer, the polystyrene block is 20-45 wt %, and the polyisoprene/butadiene block is 55-80 wt %. The polyisoprene/butadiene block has a polyisoprene unit and a polybutadiene unit. The weight ratio of the polyisoprene unit to the polybutadiene unit is 8:2 to 2:8.

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

Abstract: A clamp assembly includes at least one clamp which is provided to clamp a workpiece in electroless plating, etching, electroplating or cleaning process. The clamp includes a base, a clamping element and a limiting element. The base is mounted on a carrier and includes a guide hole and a first limiting hole which are communicated with each other. The clamping element includes a guide rod and a second limiting hole, the guide rod is inserted into the guide hole to allow the second limiting hole located on the guide hole to be communicated with the first limiting hole. The limiting element is inserted into the first and second limiting holes to integrate the base with the clamping element for clamping the workpiece.

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

Abstract: A package structure is provided herein, which includes a substrate, an integrated transistor, and an encapsulation structure. The integrated transistor is disposed on the substrate and includes a transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The transistor includes a gate, a drain, and a source. The capacitor is electrically connected to the gate, and the resistor is electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The encapsulation structure encapsulates the integrated transistor. The package structure includes a gate terminal, a drain terminal, and a source terminal.

Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.