Abstract: According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.

Abstract: A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract: According to some embodiments of the invention, semiconductor devices and DRAM cells have plug contact holes. Methods of forming the same include forming a channel-portion hole disposed in a semiconductor substrate. Lower portions of the plug contact holes between first and second word line patterns extend downward from the main surface of the semiconductor substrate, thereby reducing a contact resistance between plug patterns and electrode impurity regions. The DRAM cell having the plug contact holes can improve the current driving capability of a transistor and the refresh characteristics of a capacitor.

Abstract: According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

Abstract: Embodiments prevent or substantially reduce a short based on a misalignment caused between contacts formed vertically to a bit line in a semiconductor device. Some embodiments include forming a contact between line patterns on a semiconductor substrate on which the line patterns are surrounded with an insulation layer and each line pattern is composed of a bit line conductive layer and a capping layer. The method includes forming a masking layer on the insulation layer and the line patterns, the masking layer being for masking a portion where the contact is not formed among upper parts of the insulation layer and the line pattern; forming a contact hole between the line patterns by etching the insulation layer through use of the masking layer as an etch mask; forming a spacer in a sidewall of the contact hole; and filling up the contact hole with conductive material to form the contact.

Abstract: A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.

Abstract: Disclosed is a method of forming a self-aligned contact structure using a sacrificial mask layer. The method includes forming a plurality of parallel interconnection patterns on a semiconductor substrate. Each of the interconnection patterns has an interconnection and a mask pattern, which are sequentially stacked. Interlayer insulating layer patterns are formed to fill gap regions between the interconnection patterns. The mask patterns are partially etched to form recessed mask patterns that define grooves between the interlayer insulating layer patterns. Then, sacrificial mask patterns filling the grooves are formed. A predetermined region of the interlayer insulating layer patterns is etched using the sacrificial mask patterns as etching masks to form a self-aligned contact hole that exposes a predetermined region of the semiconductor substrate. A spacer is formed of a sidewall of the self-aligned contact hole, and a plug surrounded by the spacer is formed in the self-aligned contact hole.

Abstract: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract: According to some embodiments of the invention, bit lines are formed using a multi-layered hard mask and BC nodes are separated by forming line-type BCs in the same direction of gate lines. Thus, a narrowing of shoulders between the bit lines and the BCs can be prevented, and spacers can be formed of a low k-dielectric silicon oxide, thereby lowering parasitic capacitance.

Abstract: A polishing head and a chemical mechanical polishing apparatus having the polishing head including a plate having vacuum holes for transferring vacuum pumping force; a porous film having holes corresponding to the vacuum holes and attached to a lower surface of the plate; a retainer ring attached to the lower surface of the plate at an edge portion thereof and having a sloped surface; a clamp ring attached to the lower surface of the plate adjacent the retainer ring for clamping the retainer ring; an adjusting ring having a sloped surface parallel and in contact with the sloped surface of the retainer ring, the adjusting ring being installed between the retainer ring and the plate; and a diameter adjusting device for adjusting a diameter of the adjusting ring by moving the adjusting ring along the sloped surface of the retainer ring, thereby adjusting a height of the retainer ring.

Abstract: A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.

Abstract: A polishing head and a chemical mechanical polishing apparatus having the polishing head including a plate having vacuum holes for transferring vacuum pumping force; a porous film having holes corresponding to the vacuum holes and attached to a lower surface of the plate; a retainer ring attached to the lower surface of the plate at an edge portion thereof and having a sloped surface; a clamp ring attached to the lower surface of the plate adjacent the retainer ring for clamping the retainer ring; an adjusting ring having a sloped surface parallel and in contact with the sloped surface of the retainer ring, the adjusting ring being installed between the retainer ring and the plate; and a diameter adjusting device for adjusting a diameter of the adjusting ring by moving the adjusting ring along the sloped surface of the retainer ring, thereby adjusting a height of the retainer ring.

Abstract: A method of forming a semiconductor device that includes cleaning a substrate after forming a tungsten pattern thereon, comprises forming a tungsten layer on a substrate, etching the tungsten layer to form a tungsten pattern, and performing a cleaning process on the substrate having the tungsten pattern using a cleaning solution of a water solution containing 0.1 to 0.4 wt % fluoric acid and 0.5 to 2 wt % hydrogen peroxide. By using the method of the present invention, metal polymers and oxidized slurry residue generated while forming the tungsten pattern may be completely removed without attacking the tungsten pattern.

Abstract: A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.