Patents by Inventor Cheol Kyu Bok

Cheol Kyu Bok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140017889
    Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.
    Type: Application
    Filed: November 16, 2012
    Publication date: January 16, 2014
    Applicant: SK HYNIX INC.
    Inventors: Ki Lyoung LEE, Cheol Kyu BOK, Won Kyu KIM
  • Patent number: 8481429
    Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 9, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Heon Kim, Cheol Kyu Bok
  • Publication number: 20120289051
    Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.
    Type: Application
    Filed: January 10, 2012
    Publication date: November 15, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jae Heon KIM, Cheol Kyu Bok
  • Patent number: 8304174
    Abstract: A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok
  • Patent number: 8202683
    Abstract: A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keun Do Ban
  • Publication number: 20120009523
    Abstract: A method for forming a contact hole of a semiconductor device, includes forming a hard mask over an etch target layer, forming a first line pattern over the hard mask, forming a second line pattern over the hard mask and the first line pattern in a direction crossing the first line pattern, forming a mesh-type hard mask pattern by etching the hard mask using the first and second line patterns as etch barriers, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.
    Type: Application
    Filed: October 1, 2010
    Publication date: January 12, 2012
    Inventors: Sung-Kwon LEE, Cheol-Kyu Bok, Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang
  • Publication number: 20110256723
    Abstract: A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an etch layer, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at both sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, and forming a pad pattern over the second spacer. As a result, a line-and-space pattern such as a control gate of the NAND flash memory and a pad portion coupled to a drain contact in an X-decoder of a peripheral circuit region can be easily implemented.
    Type: Application
    Filed: December 29, 2010
    Publication date: October 20, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung LEE, Cheol Kyu Bok, Jung Hyung Lee
  • Patent number: 8003540
    Abstract: A method for manufacturing a semiconductor device includes forming an underlying layer over a semiconductor substrate; forming a hard mask layer over the underlying layer; forming first etch patterns over the hard mask layer; forming second etch patterns between the first photoresist patterns; etching the hard mask layer using the first and second etch patterns as an etch mask to form a hard mask pattern; and etching the underlying layer using at least the hard mask pattern. The first and second etch patterns are formed on the same layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 23, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheol Kyu Bok
  • Patent number: 7989145
    Abstract: A method for forming a fine pattern of a semiconductor device comprises forming a spin-on-carbon layer over an underlying layer, forming an anti-reflection pattern including a silicon containing polymer with a first etching mask pattern, forming a photoresist pattern including a silicon containing polymer with a second etching mask pattern between elements of the first etching mask pattern, and etching the spin-on-carbon layer with the etching mask patterns to reduce the process steps and the manufacturing cost, thereby obtaining a uniform pattern profile.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok
  • Patent number: 7972766
    Abstract: A method for forming a fine pattern of a semiconductor device comprises: forming anti-reflection coating patterns over an underlying layer of a semiconductor substrate using an anti-reflection coating composition comprising a silicon-containing polymer; forming a photoresist pattern between the anti-reflection coating patterns using a photoresist composition comprising a silicon-containing polymer; and patterning the underlying layer using the photoresist patterns as an etching mask.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheol Kyu Bok
  • Patent number: 7910291
    Abstract: A method for manufacturing a semiconductor device using an immersion lithography process is disclosed. The immersion lithography process includes forming a photoresist film over an underlying layer of a semiconductor substrate; exposing the photoresist film to light without using an exposure mask; and performing an exposure process using an exposure mask. After exposure using the immersion lithography, a water mark generated from the exposure layer consumes a part of the acid of the exposure layer but the residual acid remains in the exposure layer to prevent generation of pattern defects such as T-top or pattern bridges.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Kyu Bok, Hyun Sook Jun, Tae Seung Eom
  • Patent number: 7838201
    Abstract: A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Chang Jung, Cheol Kyu Bok, Chang Moon Lim, Seung Chan Moon
  • Publication number: 20100248153
    Abstract: A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern lo is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 30, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keun Do Ban
  • Patent number: 7776747
    Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching the first hard mask layer by using the spacer and the second hard mask layer pattern as an etching mask to form a first hard mask layer pattern, forming a first insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer pattern and the underlying first hard mask layer pattern to form a third hard mask layer pattern, removing the first insulating film and the spacer, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask to form a fine pattern.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: August 17, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Jun Hyeub Sun
  • Patent number: 7615497
    Abstract: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Kyu Bok, Keun Do Ban
  • Patent number: 7576009
    Abstract: A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keun Do Ban
  • Publication number: 20090191709
    Abstract: A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure.
    Type: Application
    Filed: April 8, 2009
    Publication date: July 30, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jae Chang Jung, Cheol Kyu Bok, Chang Moon Lim, Seung Chan Moon
  • Publication number: 20090170336
    Abstract: A method for forming a pattern of a semiconductor device comprises forming a spacer with an oxide film in a SPT process, and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is transcribed in a lower portion, thereby facilitating control of critical dimension in etching the underlying layer so as to improve a characteristic of the device. A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok
  • Publication number: 20090170035
    Abstract: A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.
    Type: Application
    Filed: June 29, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung LEE, Cheol Kyu Bok
  • Publication number: 20090170322
    Abstract: A method for manufacturing a semiconductor device including a vertical transistor comprises: depositing a n-layered (here, n is an integer ranging from 2 to 6) mask film over a semiconductor substrate; forming a photoresist pattern over the n-layered mask film; etching the mask film with the photoresist pattern as an etching mask until the mth layer (here, m=n?1) mask film is exposed to form a trench; filling an insulating film in the trench; removing the mask film of the insulating film to form an insulating film pattern; and patterning the mth layer mask film with the insulating film pattern as an etching mask until the semiconductor substrate is exposed.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Cheol Kyu Bok