Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: The present invention relates to a three-dimensional resistive switching memory device including a plurality of memory cells. A three-dimensional resistive switching memory device according to an embodiment comprises a plurality of memory cells. Each memory cell comprises, a semiconductor channel layer comprising a metal oxide extended in a vertical direction on the substrate; a variable resistance layer contacting one side of the semiconductor channel layer and extended in the vertical direction; and a plurality of gate structures having a gate electrode disposed on the other side opposite to the one side of the semiconductor channel layer and defining the plurality of memory cells serially connected to each other along the vertical direction, and a gate insulating film arranged between the gate electrode and the semiconductor channel layer.

Abstract: Disclosed is a method of forming a chalcogenide-based thin film using an atomic layer deposition (ALD) process including forming a Ge—Te-based material, the forming of the Ge—Te-based material may include a first operation of supplying, into a reaction chamber provided with a substrate, a first source gas including a Ge precursor with Ge having an oxidation state of +2, a second operation of supplying a first purge gas into the reaction chamber, a third operation of supplying, into the reaction chamber, a second source gas including a Te precursor and a first co-reactant gas for promoting a reaction between the Ge precursor and the Te precursor, and a fourth operation of supplying a second purge gas into the reaction chamber.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: Provided are a semiconductor memory device including a capacitor and a method of fabricating the same. The capacitor may include a plurality of contacts that are electrically connected to the switching device, exposed on the top surface of a substrate, and are arranged in a first direction and a second direction different from the first direction, and the first direction and the second direction are parallel to the substrate; mold insulators that are formed on the substrate between the contacts adjacent to one another in the first direction from among the plurality of contacts, are formed to have a predetermined thickness and have a predetermined width in the second direction, and extend in a direction vertical to the substrate; bottom electrodes that have a vertical plate-like structure, are provided on and supported by sidewalls of the mold insulators, and are electrically and respectively connected to the plurality of contacts.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.

Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode; and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode; and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament. which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode, and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

Abstract: The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.

Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode, and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

Abstract: Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.

Abstract: Provided are a semiconductor memory device including a capacitor and a method of fabricating the same. The capacitor may include a plurality of contacts that are electrically connected to the switching device, exposed on the top surface of a substrate, and are arranged in a first direction and a second direction different from the first direction, and the first direction and the second direction are parallel to the substrate; mold insulators that are formed on the substrate between the contacts adjacent to one another in the first direction from among the plurality of contacts, are formed to have a predetermined thickness and have a predetermined width in the second direction, and extend in a direction vertical to the substrate; bottom electrodes that have a vertical plate-like structure, are provided on and supported by sidewalls of the mold insulators, and are electrically and respectively connected to the plurality of contacts.

Abstract: Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.