Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.

Abstract: A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjac

Abstract: An image sensor and fabricating method thereof are provided. The image sensor can include a color filter on a semiconductor substrate, a microlens on the color filter layer, and a carbon-doped low temperature oxide layer on the microlens.

Abstract: A method of forming a device isolation film for a semiconductor device comprising forming a trench on a silicon semiconductor substrate, rounding an upper corner of the trench using an in-situ plasma method, filling the trench by forming an insulating layer over the silicon semiconductor substrate, and forming a shallow trench isolation area by performing a planarization process on the insulating layer so as to expose the silicon semiconductor substrate.

Abstract: A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer.

Abstract: A flash memory device is disclosed including: a device isolation layer and an active area formed on a semiconductor substrate in which a source plate and a bit line area are defined; a memory gate formed over the active area of the bit line area; a control gate formed on the semiconductor substrate including the memory gate; a common source area and a drain area disposed on both sides of the control gate; and a common source line contact formed over the common source area of the semiconductor substrate at the active area of the source plate, wherein the active area of the source plate is formed having the same interval with the active area of the bit line area, and the control gate is formed to cross the source plate and the bit line area disposed at both sides of the source plate.

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.

Abstract: A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjac

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include a device isolation layer and/or an active area formed on and/or over a semiconductor substrate. A flash memory device may include a memory gate formed on and/or over an active area and/or a control gate formed on and/or over a semiconductor substrate including a memory gate. Active areas may be formed having substantially the same interval with bit lines. A common source line area where a common source line contact may be formed may include a bridge formed between active areas. Neighboring active areas may be connected.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can include transistor circuitry on a substrate, and a photodiode arranged above the transistor circuitry. The photodiode can include carbon nanotubes and a conductive polymer layer on the carbon nanotubes. A transparent conducting electrode can be provided on the carbon nanotubes.

Abstract: An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include at least one circuit element. A bottom electrode and a first conductive layer may be sequentially formed over the substrate. A strained intrinsic layer may be formed over the first conductive layer. A second conductive layer may be formed over the strained intrinsic layer. An upper electrode may be formed over the second conductive layer.

Abstract: A microlens for an image sensor fabricated using a seed layer and a method for fabrication of the same that does not involve a reflow process. The method of fabricating a microlens includes forming a seed layer pattern on a wafer, rounding the corner portions of the seed layer pattern by applying plasma, and then depositing an oxide film on the seed layer pattern.

Abstract: A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material. The method for forming a metal line of a semiconductor device includes forming a lower metal line layer on a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on an entire surface including the lower metal line layer, forming a plasma layer by treating a surface of the interlayer dielectric layer with plasma, forming a photoresist pattern on the plasma layer, forming a via hole using the photoresist pattern as a mask to open the lower metal line layer, and forming a via contact by burying a metal material in the via hole.

Abstract: An image sensor that includes a contact plug formed in the substrate; a lower electrode formed on the contact plug; a photo diode formed on the lower electrode, the photo diode having a carbon nanotube provided therein; and an upper electrode formed on the photo diode. The photo diode can function as a color photo diode 160 that can transfer electrons or holes using the carbon nanotube while also functioning as a color filter.

Abstract: An image sensor includes a photo diode formed over a semiconductor substrate. At least one IMD layer is formed on the semiconductor substrate. A dielectric medium fills a through-hole formed in the IMD layer over the photo diode. The dielectric medium may be made with materials with a higher refractive index than the materials forming the IMD layer.

Abstract: A semiconductor device includes a low-k layer formed over a semiconductor device; a first TEOS film formed over the low-k layer; a SiCN layer formed over the first TEOS film; an undoped silicate glass film formed over the SiCN layer; a nitride film formed over the USG film; a second TEOS film formed over the nitride film; a first metal interconnect extending from the low-k layer to the undoped silicate glass film; and a second metal interconnect extending from the nitride film to the second TEOS film, wherein the first metal interconnect and the second metal interconnect are electrically connected and a wire is bonded to the second metal interconnect.

Abstract: A method of manufacturing a semiconductor device includes a device isolation layer. In the method, a hard mask may be formed on a semiconductor substrate, and the semiconductor substrate may be etched using the hard mask as a mask to form a trench. The hard mask may be removed, and a device isolation layer may be formed in the trench. A shallow trench isolation pattern having an excellent layer quality may be formed by reducing an aspect ratio of the trench in the semiconductor device and gap-filling a dielectric. Thus, the number of defects may be decreased.

Abstract: Embodiments relate to a semiconductor device that may include a semiconductor substrate including a cell area and a pad area, a first insulating layer on and/or over the semiconductor substrate, and a first interconnection trench formed in the first insulating layer on and/or over a cell area having a first width. It may also include a first pad trench formed in the first insulating layer on and/or over the pad area and having a second width wider than the first width, and a first metal interconnection formed in the first interconnection trench and a first pad formed in the first pad trench. It may further include a second insulating layer on and/or over the first insulating layer, a second interconnection trench, exposing the first metal interconnection, and a second pad exposing the first pad and having a position and width substantially identical to that of the first pad trench.

Abstract: A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer.

Abstract: A microlens for an image sensor fabricated using a seed layer and a method for fabrication of the same that does not involve a reflow process. The method of fabricating a microlens includes forming a seed layer pattern on a wafer, rounding the corner portions of the seed layer pattern by applying plasma, and then depositing an oxide film on the seed layer pattern.