Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier layer on at least the bottom surface, the side surface, and a part of the top surface, removing the diffusion barrier layer from at least a part of the bottom surface, depositing a seed layer on at least the part of the bottom surface and the diffusion barrier layer, and depositing an electrode layer on the seed layer.

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

Abstract: A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench.

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A system allowing a user of a browser program on a computer connected to an open distributed hypermedia system to access and execute an embedded program object. The program object is embedded into a hypermedia document much like data objects. The user may select the program object from the screen. Once selected the program object executes on the user's (client) computer or may execute on a remote server or additional remote computers in a distributed processing arrangement. After launching the program object, the user is able to interact with the object as the invention provides for ongoing interprocess communication between the application object (program) and the browser program. One application of the embedded program object allows a user to view large and complex multi-dimensional objects from within the browser's window. The user can manipulate a control panel to change the viewpoint used to view the image.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench.

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.