Patents by Inventor Cheong Ang
Cheong Ang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20020151108Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: ApplicationFiled: June 10, 2002Publication date: October 17, 2002Inventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong
-
Patent number: 6465296Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: GrantFiled: June 10, 2002Date of Patent: October 15, 2002Assignee: Chartered Semiconductor Manufacturing LTDInventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong
-
Patent number: 6455384Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions.Type: GrantFiled: October 9, 2001Date of Patent: September 24, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Fong Quek, Jun Song, Xing Yu
-
Publication number: 20020115239Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: ApplicationFiled: April 24, 2002Publication date: August 22, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Song Jun, Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek
-
Publication number: 20020089031Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: ApplicationFiled: January 8, 2001Publication date: July 11, 2002Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek, Jun Song
-
Patent number: 6416909Abstract: A new process for fabricating an alternating phase-shifting photomask having an alignment monitor is described. An opaque layer is provided overlying a substrate. The opaque layer is patterned to provide a mask pattern. A phase-shifting pattern is formed on the substrate wherein a portion of the phase-shifting pattern comprises an alignment monitor whereby alignment between the mask pattern and the phase-shifting pattern can be tested.Type: GrantFiled: July 18, 2000Date of Patent: July 9, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue Fong Quek, Ting Cheong Ang, Swee Hong Choo, Sang Yee Loong
-
Patent number: 6406975Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.Type: GrantFiled: November 27, 2000Date of Patent: June 18, 2002Assignee: Chartered Semiconductor Manufacturing Inc.Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
-
Patent number: 6406948Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.Type: GrantFiled: July 13, 2000Date of Patent: June 18, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Song Jun, Ting Cheong Ang, Sang Yee Loong, Shyue Fong Quek
-
Patent number: 6406994Abstract: A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material.Type: GrantFiled: November 30, 2000Date of Patent: June 18, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Fong Quek, Yee Chong Wong, Sang Yee Loong
-
Patent number: 6399431Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.Type: GrantFiled: March 21, 2000Date of Patent: June 4, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jun Song, Ting Cheong Ang, Shyue Fong Quek, Sang Yee Loong
-
Patent number: 6380106Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.Type: GrantFiled: November 27, 2000Date of Patent: April 30, 2002Assignee: Chartered Semiconductor Manufacturing Inc.Inventors: Seng Keong Victor Lim, Young-way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
-
Publication number: 20020048884Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal which forms the semiconductor channel in the substrate. Contacts are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.Type: ApplicationFiled: February 22, 2000Publication date: April 25, 2002Inventors: Shyue Fong Quek, Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong
-
Patent number: 6376319Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions.Type: GrantFiled: October 9, 2001Date of Patent: April 23, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Fong Quek, Jun Song, Xing Yu
-
Patent number: 6376379Abstract: A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.Type: GrantFiled: February 1, 2000Date of Patent: April 23, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shyue Fong Quek, Ting Cheong Ang, Jun Song, Sang Yee Loong
-
Publication number: 20020022328Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.Type: ApplicationFiled: September 6, 2001Publication date: February 21, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Ting Cheong Ang, Shyue Fong Quek, Sang Yee Loong, Jun Song
-
Publication number: 20020013032Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions.Type: ApplicationFiled: October 9, 2001Publication date: January 31, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Ting Cheong Ang, Shyue Fong Quek, Jun Song, Xing Yu
-
Patent number: 6329253Abstract: A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps.Type: GrantFiled: November 5, 1999Date of Patent: December 11, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jun Song, Yonqzang Zhang, Shyue Fong Quek, Ting Cheong Ang, Jun Cai, Puay Ing Ong
-
Patent number: 6319783Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions.Type: GrantFiled: November 19, 1999Date of Patent: November 20, 2001Assignee: Chartered Semiconductor Manufatcuring Ltd.Inventors: Ting Cheong Ang, Shyue Pong Quek, Jun Song, Xing Yu
-
Patent number: 6303414Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.Type: GrantFiled: July 12, 2000Date of Patent: October 16, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Fong Quek, Sang Yee Loong, Jun Song
-
Patent number: 6300172Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls.Type: GrantFiled: October 1, 1999Date of Patent: October 9, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Pong Quek, Lap Chan, Sang Yee Loong