Abstract: A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Abstract: A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals together with associated parity bits for writing into an addressed storage location of memory. During the write cycle, error encoder circuits generate check code bits from the multibyte data and parity bits which are coded to signal selectively the presence of a multibyte uncorrectable error condition in accordance with the parity bits from a device. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check bits read out from an addressed location are operative to generate a number of syndrome bits.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: A memory controller couples to a number of memory modules and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command from a requesting device. This command when decoded causes the controller to read out from the memory modules a predetermined number of words starting with any word boundary at the location specified by the stored address portion.

Abstract: Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corresponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.

Abstract: A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.

Abstract: A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.

Abstract: A memory subsystem couples to a double wide word bus in common with a number of central processing units for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes common control circuits, timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom into a pair of data registers. The outputs of the data registers couple to the inputs of a pair of output multiplexer circuits. The outputs of the multiplexer circuits are connected to provide double wide output to the double wide word bus.

Abstract: Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the soft error rewrite control apparatus enables the read out of information stored within each module location, the correction of any single bit errors contained therein and the rewriting of the corrected information back into such location. Diagnostic apparatus is further included which is connected to place the memory system in a state for testing and verifying the operation of the soft error control apparatus. Also, the diagnostic apparatus is connected to condition the soft error control apparatus for operating in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

Abstract: A memory subsystem couples to a single word bus in common with a central processing unit for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which specifies the row of chips to be accessed within a first one of the pair of memory units. The subsystem further includes control circuits, common timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed.

Abstract: A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches.

Abstract: A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

Abstract: A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit.