Patents by Inventor Chi-An Wang
Chi-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120139Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.Type: ApplicationFiled: December 17, 2024Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai CHENG, Liang-Yi CHEN, Chi-An WANG, Kuan-Chung CHEN, Chih-Wei LEE
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Patent number: 12176390Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.Type: GrantFiled: February 23, 2022Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Liang-Yi Chen, Chi-An Wang, Kuan-Chung Chen, Chih-Wei Lee
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Patent number: 12089394Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.Type: GrantFiled: September 19, 2022Date of Patent: September 10, 2024Assignee: Winbond Electronics Corp.Inventors: Chi-An Wang, Kai Jen, Wei-Che Chang
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Publication number: 20230268390Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai CHENG, Liang-Yi CHEN, Chi-An WANG, Kuan-Chung CHEN, Chih-Wei LEE
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Publication number: 20230012828Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Applicant: Winbond Electronics Corp.Inventors: Chi-An Wang, Kai Jen, Wei-Che Chang
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Patent number: 11495605Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.Type: GrantFiled: December 15, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventors: Chi-An Wang, Kai Jen, Wei-Che Chang
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Publication number: 20220068939Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.Type: ApplicationFiled: December 15, 2020Publication date: March 3, 2022Applicant: Winbond Electronics Corp.Inventors: Chi-An Wang, Kai Jen, Wei-Che Chang
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Patent number: 11024603Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.Type: GrantFiled: April 17, 2019Date of Patent: June 1, 2021Assignee: POWERTECH TECHNOLOGY INC.Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
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Patent number: 10424526Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.Type: GrantFiled: October 13, 2017Date of Patent: September 24, 2019Assignee: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu, Wen-Hsiung Chang
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Publication number: 20190244934Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
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Patent number: 10354978Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.Type: GrantFiled: January 10, 2018Date of Patent: July 16, 2019Assignee: POWERTECH TECHNOLOGY INC.Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
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Publication number: 20190214366Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Applicant: Powertech Technology Inc.Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
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Publication number: 20190214367Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Applicant: Powertech Technology Inc.Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu, Li-Chih Fang
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Patent number: 10276553Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.Type: GrantFiled: October 19, 2017Date of Patent: April 30, 2019Assignee: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu
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Patent number: 10177060Abstract: A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the substrate. The encapsulant encapsulates the chip and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the substrate. The patterned metal layer s disposed on the encapsulant. The patterned metal layer includes at least one concave portion and at least one convex portion defined by the concave portion. The convex portion faces the encapsulant. The adhesion layer is disposed between the patterned metal layer and the encapsulant. The adhesion layer is filled in the concave portion.Type: GrantFiled: July 10, 2017Date of Patent: January 8, 2019Assignee: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu
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Patent number: 10170458Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.Type: GrantFiled: October 13, 2017Date of Patent: January 1, 2019Assignee: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu
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Publication number: 20180114782Abstract: A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.Type: ApplicationFiled: September 28, 2017Publication date: April 26, 2018Applicant: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu, Yuan-Fu Lan, Hsien-Wen Hsu
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Publication number: 20180114704Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.Type: ApplicationFiled: October 13, 2017Publication date: April 26, 2018Applicant: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu
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Publication number: 20180114736Abstract: A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the substrate. The encapsulant encapsulates the chip and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the substrate. The patterned metal layer s disposed on the encapsulant. The patterned metal layer includes at least one concave portion and at least one convex portion defined by the concave portion. The convex portion faces the encapsulant. The adhesion layer is disposed between the patterned metal layer and the encapsulant. The adhesion layer is filled in the concave portion.Type: ApplicationFiled: July 10, 2017Publication date: April 26, 2018Applicant: Powertech Technology Inc.Inventors: Chi-An Wang, Hung-Hsin Hsu
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Publication number: 20180114786Abstract: A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.Type: ApplicationFiled: February 3, 2017Publication date: April 26, 2018Inventors: Hung-Hsin Hsu, Chi-An Wang