STACKED PACKAGE INCLUDING EXTERIOR CONDUCTIVE ELEMENT AND A MANUFACTURING METHOD OF THE SAME
A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
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The present invention relates to a semiconductor package, and in particular to a stacked package and a manufacturing method of the same.
2. Description of the Prior ArtsStacking a plurality of chips has been implemented in various semiconductor packages to achieve miniaturization of component integration. The wire bonding method and the through silicon via (TSV) with micro bump are conventional ways to provide electrical interconnection between the stacked chips and the external terminals. However, the conventional ways have following disadvantages.
When the chips are connected to the external terminals by wire bonding, the intervals between the bonding wires need to be preserved to avoid contacts between the adjacent bonding wires. The intervals inevitably increase the size of the conventional stacked package. Thus, the conventional stacked package with bonding wires does not easily achieve miniaturization. In addition, the wire bonding process takes a lot of time since all of the wires for one conventional stacked package cannot be bonded simultaneously. Therefore, the unit per hour (UPH) of the conventional stacked package manufactured by the wire bonding process is relatively low.
When the chips are connected to each other by the TSV and the micro bumps, the TSV increases stacked heights and processing complexity leading to larger package thickness and lower manufacturing yield. In addition, the requirements for the precision of alignment and locating among the micro bumps are very high. When the dimension of the conventional stacked packages become larger and larger, the position shift of the micro bumps becomes greater and greater leading to poor packaging yield.
To overcome the shortcomings, the present invention provides a stacked package and a manufacturing method of the same to mitigate or to obviate the aforementioned problems.
SUMMARY OF THE INVENTIONThe main objective of the present invention is to provide a stacked package and a manufacturing method of the same that has higher UPH and better reliability. The stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated.
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In one embodiment as shown in
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In summary, the cut edge 130 of each exterior conductive element 13 may be the exterior trace 132 as shown in
An exemplary embodiment shown in
A manufacturing method of a stacked package in accordance with the present invention are illustrated from
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With the cut edges 130 exposed on the at least one of the lateral side of the chip package 10, the electrical connections between the chips 11 and the electrical connection between the chips 10 and the external terminals 82 are achieved by the redistribution layer 80 formed on the cut edges 130 on the at least one of the lateral sides. Thus, the process for forming the electrical connections of the manufacturing method as described is simplified to enhance the reliability and the UPH for manufacturing the stacked package as described. Moreover, the requirement of the precision for stacking the chip packages 10 is relatively low since the chip packages 10 are aligned after dicing process as shown in
According to an embodiment of the present invention, the stacked package 90 may have, but not limited to, following structures, and the manufacturing method of the stacked package may have accordingly steps.
In one embodiment as shown in
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In one embodiment as shown in
Another embodiment of a manufacturing method of a stacked package in accordance with the present invention includes, but not limited to, following steps:
After the steps are performed as shown in
With further reference to
Yet another embodiment of a manufacturing method of a stacked package in accordance with the present invention includes, but not limited to, following steps:
The chip packages 10C have cut edges 130C exposed on two lateral sides as shown in
With reference to
The electrical connection between the chips 10, the cut edges 130 on the second lateral side, the redistribution layer 80 and the UBM layer 81 is formed after the carrier 50 and the adhesive film 51 are detached. With further reference to
In some embodiment, with reference to
With the stacked package 90D has the external terminals 82 on dual sides, stacking with other semiconductor structures, passive components and so on are is more easily.
Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and features of the invention, the disclosure is illustrative only. Changes may be made in the details, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Claims
1. A stacked package comprising:
- a plurality of chip packages stacked on each other, and each chip package of the plurality of chip packages having two lateral sides; a chip having an active surface and a back surface opposite to the active surface, wherein the back surface of each chip package faces the active surface of an adjacent chip package; a passivation layer formed on the active surface of the chip; and an exterior conductive element formed on the active surface of the chip and having a cut edge exposed on at least one of the two lateral sides, each of the two lateral sides comprising a lateral side of the chip, a lateral side of the passivation layer, and the cut edge;
- an encapsulant encapsulating the chip packages and having an opening expose the at least one of the two lateral sides;
- at least one dielectric layer formed on the at least one of the two lateral sides and having patterned recess areas expose the cut edges on the at least one of the two lateral sides; and
- at least one redistribution layer formed on the at least one dielectric layer, filled with the patterned recess areas of the at least one dielectric layer and electrically connecting to the cut edges on the at least one of the two lateral sides.
2. The stacked package as claimed in claim 1, wherein
- each chip package has two cut edges exposed respectively on both of the two lateral sides;
- an amount of the at least one dielectric layer is two and the two dielectric layers are formed respectively on the cut edges on both of the two lateral sides; and
- an amount of the at least one redistribution layer is two and the two redistribution layers are formed respectively on the two dielectric layers and connect respectively to the cut edges on both of the two lateral sides.
3. The stacked package as claimed in claim 2 further comprising
- two additional dielectric layers formed respectively on the two redistribution layers and having a plurality of gaps to reveal the cut edges on the two lateral sides;
- two under bump metallurgy layers formed respectively on the two additional dielectric layers and respectively connect to the two redistribution layers; and
- a plurality of external terminals formed on and connecting to the two bump metallurgy layers.
4. The stacked package as claimed in claim 1, wherein
- the exterior conductive element has a bond pad formed on the active surface and encapsulated by the passivation layer; and an exterior trace formed on the bond pad and extending out the passivation layer;
- the cut edge of the exterior conductive element is disposed on an end of the exterior trace; and
- the chip package further comprises a dielectric layer formed on the passivation layer and the exterior trace.
5. The stacked package as claimed in claim 1, wherein
- the exterior conductive element has a conductive pad formed on the active surface and encapsulated by the passivation layer; and
- the cut edge of the exterior conductive element is disposed on an end of the conductive pad.
6. The stacked package as claimed in claim 1, wherein
- the exterior conductive element has a bond pad formed on the active surface and encapsulated by the passivation layer; and a through silicon via formed in the chip and connecting to the bond pad; and
- the cut edge of the exterior conductive element is disposed on an end of the through silicon via.
7. The stacked package as claimed in claim 1, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is formed on the cut edges on the at least one of the two lateral sides, and the second dielectric layer is formed between the at least one redistribution layer and the external terminals.
8. The stacked package as claimed in claim 1 further comprising at least one under bump metallurgy layer, wherein
- the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer;
- the first dielectric layer is formed on the cut edges on the at least one of the two lateral sides;
- the at least one redistribution layer is formed on the first dielectric layer;
- the second dielectric layer is formed on the at least one redistribution layer;
- the at least one under bump metallurgy layer is formed on the second dielectric layer and connects to the at least one redistribution layer; and
- external terminals are formed respectively on and connecting to the at least one under bump metallurgy layer.
9. The stacked package as claimed in claim 1, wherein the plurality of chip packages stacked on each other by using a plurality of adhesives attached respectively between adjacent chip packages.
10. A manufacturing method of a stacked package comprising steps of:
- stacking a plurality of chip packages on a carrier, wherein each chip package has a two lateral sides, a chip having an active surface and a back surface opposite to the active surface and an exterior conductive element formed on the active surface of the chip and having a cut edge exposed on at least one of the lateral sides, wherein the back surface of one chip package faces the active surface of the adjacent chip package and one of the lateral sides facing the carrier;
- encapsulating the chip packages on the carrier by a encapsulant;
- revealing the cut edges on the at least one of the lateral sides;
- forming at least one dielectric layer on the at least one of the lateral sides and revealing the cut edges on the at least one of the lateral sides;
- forming at least one redistribution layer on the at least one dielectric layer, wherein the at least one redistribution layer electrically connects to the cut edges on the at least one of the lateral sides; and
- performing singulation to form a plurality of the stacked packages.
11. The manufacturing method as claimed in claim 10 further comprising a step of detaching the carrier, wherein
- the lateral sides of the chip package include a first lateral side and a second lateral side;
- the cut edges of each chip package are exposed on the first lateral side;
- in the step of stacking a plurality of chip packages on a carrier, the second lateral sides of the chip packages face the carrier;
- in the step of revealing the cut edges, the encapsulant is partially removed to reveal the cut edges on the first lateral side; and
- the step of detaching the carrier is performed before the step of performing singulation.
12. The manufacturing method as claimed in claim 10, wherein
- the lateral sides of the chip package include a first lateral side and a second lateral side;
- the cut edges of each chip package are exposed on the first lateral side;
- in the step of stacking a plurality of chip packages on a carrier, the first lateral sides of the chip packages face the carrier; and
- in the step of revealing the cut edges, the carrier is detached to reveal the cut edges on the first lateral side.
13. The manufacturing method as claimed in claim 10, wherein
- the lateral sides of the chip package include a first lateral side and a second lateral side;
- the cut edges of each chip package are exposed both on the first and second lateral sides;
- in the step of stacking a plurality of chip packages on a carrier, the second lateral sides of the chip packages face the carrier;
- in the step of revealing the cut edges, the encapsulant is partially removed to reveal the cut edges on the first lateral side;
- in the step of forming at least one dielectric layer, the at least one dielectric layer is formed on the cut edges on the first lateral side;
- in the step of forming at least one redistribution layer, the at least one redistribution layer electrically connects to the cut edges on the first lateral side; and
- the manufacturing method further comprising steps of after forming at least one redistribution layer, detaching the carrier; forming at least one additional dielectric layer on the second lateral sides and revealing the cut edges on the second lateral sides; forming at least one additional redistribution layer on the at least one additional dielectric layer, wherein the at least one additional redistribution layer electrically connect to the cut edges on the second lateral sides; and forming a plurality of external terminals on the at least one redistribution layer, wherein the external terminals are formed and connect respectively to the at least one redistribution layer and the at least one additional redistribution layer.
14. The manufacturing method as claimed in claim 10, wherein in the step of stacking a plurality of chip packages on a carrier comprises steps of:
- forming a plurality of chip stacks by stacking a plurality of chip packages;
- encapsulating the chip stacks;
- forming a plurality of chip encapsulations by dicing the chip stacks; and
- arranging the chip encapsulations on the carrier.
15. The manufacturing method as claimed in claim 14, wherein in the step of forming a plurality of chip stacks, a plurality of adhesives are used to attach respectively between adjacent chip packages.
16. The manufacturing method as claimed in claim 10 further comprising steps of:
- forming at least one supplemental dielectric layer on the at least one redistribution layer; and
- forming a plurality of external terminals on the at least one supplemental dielectric layer.
17. The manufacturing method as claimed in claim 10 further comprising steps of:
- forming at least one supplemental dielectric layer on the at least one redistribution layer after the step of forming at least one redistribution layer;
- forming at least one under bump metallurgy layer on the at least one redistribution layer; and
- forming a plurality of external terminals on the at least one of the under bump metallurgy layer, wherein the external terminals are formed on and electrically connect to the at least one of the under bump metallurgy layer.
18. The manufacturing method as claimed in claim 10, wherein in the step of stacking a plurality of chip packages on a carrier, the chip packages are stacked on the carrier through an adhesive film.
Type: Application
Filed: Jan 10, 2018
Publication Date: Jul 11, 2019
Applicant: Powertech Technology Inc. (Hukou Township)
Inventors: Ming-Chih Chen (Hukou Township), Hung-Hsin Hsu (Hukou Township), Yuan-Fu Lan (Hukou Township), Chi-An Wang (Hukou Township), Hsien-Wen Hsu (Hukou Township)
Application Number: 15/867,577