Abstract: A fusion method is provided to obtain a spatiotemporal image. The present invention is based on a conventional model—a spatial and temporal adaptive reflectance fusion model (STARFM). In the present invention, top-of-atmosphere (TOA) reflectance is kept in image fusion. Furthermore, Himawari-8, a geostationary satellite having a very high temporal resolution (10 minutes), is used. The present invention uses similar spectral bands as whose used for high-spatial-resolution image in satellites like Landsat-8 and SPOT-6. The present invention combines a high spatial-resolution image with a high temporal-resolution image obtained from Himawari-8. Thus, a TOA-reflectance-based spatial-temporal image fusion method (TOA-STFM) is proposed for generating an image having high spatiotemporal resolution. The present invention can be applied for air quality monitoring.

Abstract: A sensing display apparatus includes a pixel array substrate, a sensing device substrate, and a display medium layer. The sensing device substrate includes a first substrate, a sensing device, first to third signal lines, and a shielding layer. The sensing device includes a first switching element electrically connected with the first and second signal lines, an electrically conductive layer electrically connected with the third signal line, an electrode layer electrically connected with the first switching element and a photo-sensitive layer disposed between the electrically conductive layer and the electrode layer. The shielding layer is disposed between the first to third signal lines and the pixel array substrate. The sensing display apparatus has light transmitting regions and a light shielding region surrounding the light transmitting regions. The sensing device and the first to third signal lines are disposed in the light shielding region.

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A hurdle structure includes a transverse bar, two upright poles, two support rods, and a plurality of hinge mechanisms. Each of the hinge mechanisms is mounted between the transverse bar and each of the two upright poles, and between each of the two upright poles and each of the two support rods. Each of the hinge mechanisms includes a first pivot member, and a second pivot member pivotally connected with the first pivot member. Each of the hinge mechanisms further includes an adjusting unit mounted between the first pivot member and the second pivot member. The adjusting unit includes a locking member and a positioning member. The locking member is provided with a plurality of grooves. The positioning member is provided with a projection positioned in one of the grooves of the locking member.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.

Abstract: A combination for improving intestinal micro-ecology and preventing chronic diseases includes an inulin, a galactooligosaccharide and a dietary fiber composite, wherein the ratio of the inulin, the galactooligosaccharide and the dietary fiber composite in a formula is (1-75):(1-75):(5-95). Preferably, the ratio is (10-50):(10-50):(25-50). A balanced nutritious food includes cereal flour and the ratio of the cereal flour to the combination in a formula is (50-95):(5-50). Preferably, the ratio is (70-95):(30-5). Moreover, provided is an application in preparing foods or medicaments for preventing inflammatory bowel disease, improving gastrointestinal motility and preventing constipation, preventing diabetes, preventing cardiovascular and cerebrovascular diseases, and regulating intestinal flora to enhance immune ability.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: An electrical component includes an insulating base, an insulating layer provided outside the insulating base, a shielding member provided between the insulating base and the insulating layer, and multiple conductive bodies accommodated in the insulating base. The conductive bodies include at least one power supply body. Each of the at least one power supply body is provided with a shielding layer outside the power supply body and an insulator between the power supply body and the shielding layer. The shielding layer is accommodated in the shielding member. In the electrical component, by providing a shielding layer and an insulator provided between the power supply body and the shielding layer outside the power supply body, shielding of the shielding layer from the power supply body is implemented, so as to reduce an interference of the power supply body on a signal body, thereby improving transmission quality of high-frequency signals.

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.

Abstract: A method for controlling access to a wireless Access Network (AN) by a wireless communication device. The device stores a Device Access Priority (DAP) level based on characteristics of the device. When the device has data to send, the device receives an overhead message from the AN containing a Network Access Priority (NAP) parameter defining a minimum priority level for initiating network access. The device determines whether its DAP level is equal to or greater than the NAP parameter. If not, the device periodically repeats the receiving and determining steps until the stored DAP level is determined to be equal to or greater than the NAP parameter received from the AN. When the stored DAP level is equal to or greater than the NAP parameter, the device initiates network access. The device may perform and pass a Persistence Test before transmitting the data on an access channel (ACH).

Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.

Abstract: A battery includes a battery case including a housing having side walls defining a first open end and a second open end, the battery case including a separate top cover to cover the first open end of the housing and a separate bottom cover to cover the second open end of the housing; a first electrode located within the case; a second electrode located within the case; a first terminal coupled to the first electrode and exposed outside the case; and a second terminal coupled to the second electrode and exposed outside the case.

Abstract: A radio frequency communication guiding device comprising: a generally elongated body having an elongated cavity therein arranged to house a communication circuit, wherein the communication circuit is supported within the cavity by a substrate layer arranged to place within the cavity so as to support the communication circuit within the cavity.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: Described herein are systems, methods, and software to enhance network traffic management for virtual machines. In one implementation, a host for a virtual machine may identify applications available for execution on the virtual machine from mounted application volumes and identify firewall rules for the applications. Once identified, the host may identify network traffic for the virtual machine, and forward or block the network traffic for the virtual machine based on the firewall rules.