Abstract: A computer system includes a cache unit and a first processing unit. The first processing unit runs a first program thread, and performs an instruction to store information of a signal change event into the cache unit through a cache stashing operation, where the signal change event is initiated by the first program thread for alerting a second program thread.

Abstract: The present invention discloses a method for software-hardware authentication of an electronic apparatus includes receiving a challenge string (CS) from the electronic apparatus through a challenge string input port (CSIP). The challenge string is a string of trace data generated according to some operations of software running on the electronic apparatus. An authentication result for use in an authentication process for the software to authenticate a hardware unit of the electronic apparatus or for the hardware unit to authenticate the software is generated according to the string of the trace data. The authentication process is performed according to the generated authentication result.

Abstract: A hardware configuration apparatus is provided. The hardware configuration apparatus is a part of a hardware system and the hardware system includes at least one function. The hardware configuration apparatus includes an interface unit, a resolution unit, and an output generation unit. For each function of the hardware system, the resolution unit generates a current setting corresponding to the function based on a default setting corresponding to the function and function settings of a plurality of secure configuration entries (SCEs) corresponding to the function. The interface unit is coupled to the resolution unit and a storage storing the SCEs. The interface unit provides the SCEs to the resolution unit. The output generation unit is coupled to the resolution unit. For each function of the hardware system, the output generation unit outputs a configuration signal to enable or disable the function according to the current setting corresponding to the function.

Abstract: The present invention discloses a method for software-hardware authentication of an electronic apparatus includes receiving a challenge string (CS) from the electronic apparatus through a challenge string input port (CSIP). The challenge string is a string of trace data generated according to some operations of software running on the electronic apparatus. An authentication result for use in an authentication process for the software to authenticate a hardware unit of the electronic apparatus or for the hardware unit to authenticate the software is generated according to the string of the trace data. The authentication process is performed according to the generated authentication result.

Abstract: A secure protection method executed by a processor is provided. The secure protection method includes the following steps. Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE). Ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor.

Abstract: The invention discloses a secure bus system and a bus system security method. The secure bus system includes a bus interconnect structure, a bus master, a bus device and a security control module. The security control module determines a device security attribute for the bus device. When the master security attribute of the bus master or the device security attribute of the bus device has changed, the security control module determines a security permission flag related to the bus master. When the security control module receives a bus transaction from the bus master, the security control module determines whether a security violation condition happens between the bus master and the bus device according to the security permission flag. If the security violation condition happens, the security control module triggers a security violation handling process to further restrict accessibility of the bus master to the bus device.

Abstract: An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.

Abstract: A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal.

Abstract: An information collection system is provided. The information collection system includes an information collection unit, an information initiation unit, and an information relay unit. The information collection unit includes at least one slave port, and the information collection unit responds a transaction through the slave port. The information initiation unit includes at least one master port, and the information initiation unit initiates the transaction through the master port. The information relay unit includes at least one master port and at least one slave port, and the information relay unit relays the transaction through the master port and the slave port wherein the transaction includes a write transaction. Wherein, during an identification phase, the master port of the information initiation unit delivers a header, and the slave port of the information collection unit accepts the transaction according to the header.

Abstract: An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.

Abstract: A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP.

Abstract: A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal.

Abstract: A power scaling unit (PSU) of an electronic system is provided. The PSU includes a software programming interface (SPI) and a PSM. The SPI receives a transaction through software programming. The PSM receives the transaction from the SPI and controls a power driving element (PDE) of the electronic system to change an output of the PDE provided to a function unit of the electronic system according to the transaction. The output of the PDE is an operating voltage or an operating clock signal of the function unit. The transaction includes a command defining a power scaling operation to be performed by the PSM, a parameter used by the operation, and an event mask specifying an event which triggers the operation.

Abstract: A memory module and a corresponding method for handling atomic operations in a multi-level memory system (MLMS) are provided. The memory module receives load and store operations of the atomic operations from a data processing engine (DPE) or an upper level memory module (ULMM). The memory module logs the load operation and/or forward the load operation to a lower level memory module (LLMM) according to predetermined conditions such as cacheability or whether there is a data hit or not. In addition, the memory module executes the store operation, inhibits the store operation, or forwards the store operation to an LLMM according to predetermined conditions such as cacheability, data hit, or whether there is a matching load operation logged in the memory module. The memory module and the method ensure correct, consistent and efficient execution of atomic operations for all DPEs sharing the MLMS.

Abstract: A power scaling unit (PSU) of an electronic system is provided. The PSU includes a software programming interface (SPI) and a PSM. The SPI receives a transaction through software programming. The PSM receives the transaction from the SPI and controls a power driving element (PDE) of the electronic system to change an output of the PDE provided to a function unit of the electronic system according to the transaction. The output of the PDE is an operating voltage or an operating clock signal of the function unit. The transaction includes a command defining a power scaling operation to be performed by the PSM, a parameter used by the operation, and an event mask specifying an event which triggers the operation.

Abstract: A data processing engine is provided, which includes an endian register, an endian control device, and a byte swapper. The endian register stores a plurality of endian control bits. Each endian control bit indicates the default data endianness of a type of address space accessible to the data processing engine. Each endian control bit is in either a big-endian state or a little-endian state. The endian control device is coupled to the endian register. The endian control device provides an endian signal according to the endian control bits and the instruction executed by the data processing engine. The endian signal is in either the big-endian state or the little-endian state. The byte swapper is coupled to the endian control device. The byte swapper transmits data and changes the byte order of the data when the byte order of the data is inconsistent with the state of the endian signal.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.

Abstract: An exemplary string processing method for specific byte string processing with word-related instructions includes: loading a plurality of first predetermined strings; comparing a specific string with the loaded first predetermined strings simultaneously, thereby generating a plurality of comparison results corresponding to the specific string; and generating a string processing result according to the comparison results. A string processing apparatus uses the string processing method.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.