Abstract: An organic light emitting diode display device and a manufacturing method thereof are provided. The organic light emitting diode display device includes a first flexible substrate, a second flexible substrate, a first barrier layer, a second barrier layer, an organic light emitting diode element, and a metal enclosing wall. The first barrier layer is disposed on the first flexible substrate, and the second barrier layer is disposed on the second flexible substrate. The organic light emitting diode element is disposed between the first barrier layer and the second barrier layer. The metal enclosing wall connects the first flexible substrate to the second flexible substrate and surrounds the organic light emitting diode element.

Abstract: A method for manufacturing a display is provided. A display including a supporting layer, a flexible layer and a display structure is provided. The display structure has a top side and a bottom side which are opposite to each other. One of the supporting layer and the flexible layer is disposed at the bottom side of the display structure, and the other one of the supporting layer and the flexible layer is disposed at the top side or the bottom side of the display structure. When the supporting layer and the flexible layer are both disposed at the bottom side of the display structure, the flexible layer is located between the supporting layer and the display structure.

Abstract: An element substrate comprises a flexible substrate, an element layer, a buffer layer and an interface layer. The element layer is disposed on the flexible substrate. The buffer layer is disposed on the flexible substrate. The buffer layer and the element layer are disposed on the opposite sides of the flexible substrate. The interface layer is disposed between the flexible substrate and the buffer layer and includes partial material of both of the flexible substrate and the buffer layer. A display apparatus including the element substrate and a manufacturing method of the element substrate are disclosed.

Abstract: An electronic apparatus and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate with a first surface and a second surface; an electronic unit layer disposed on the first surface of the substrate; a residue layer disposed on the second surface of the substrate, wherein a material of the residue layer comprises: a compound containing at least one functional group selected from the group consisting of aryl, nitro and ketone.

Abstract: The present invention provides a method for manufacturing a display panel, comprising the following steps: (A) providing a carrier with a separation layer formed thereon; (B) laminating a glass substrate on the hydrophobic surface of the separation layer to make the separation layer between the carrier and the glass substrate; (C) forming a display unit on the glass substrate; and (D) separating the glass substrate from the carrier and the separation layer to obtain a display panel; wherein the separation layer has a hydrophobic surface with a water contacting angle in a range from 25° to 180°.

Abstract: An organic light emitting diode display device and a manufacturing method thereof are provided. The organic light emitting diode display device includes a first flexible substrate, a second flexible substrate, a first barrier layer, a second barrier layer, an organic light emitting diode element, and a metal enclosing wall. The first barrier layer is disposed on the first flexible substrate, and the second barrier layer is disposed on the second flexible substrate. The organic light emitting diode element is disposed between the first barrier layer and the second barrier layer. The metal enclosing wall connects the first flexible substrate to the second flexible substrate and surrounds the organic light emitting diode element.

Abstract: A thin film transistor substrate, a display apparatus using the same and a manufacturing method thereof are provided. The display apparatus includes a thin film transistor substrate, a top substrate and a display medium layer. The thin film transistor substrate includes a composite plate and several thin film transistors. The composite plate includes a core material structure and two insulation structures. The core material structure includes a metal layer. The two insulation structures are respectively disposed at two sides of the core material structure so as to sandwich the core material structure therebetween. The thin film transistors are disposed on the composite plate. The display medium layer is disposed between the thin film transistor substrate and the top substrate.

Abstract: A method for reducing transmission latency and a control module thereof are operated inside a host and at an external USB device. The method includes following steps: when the host receives an NRDY packet, storing a first data segment to be transferred by the host at the buffer storage unit inside the host; when the host receives an ERDY packet, capturing the first data segment stored at the buffer storage unit; and transferring the first data segment to the external USB device.

Abstract: A display including a supporting layer, a flexible layer and a display structure is provided. The display structure has a top side and a bottom side which are opposite to each other. One of the supporting layer and the flexible layer is disposed at the bottom side of the display structure, and the other one of the supporting layer and the flexible layer is disposed at the top side or the bottom side of the display structure. When the supporting layer and the flexible layer are both disposed at the bottom side of the display structure, the flexible layer is located between the supporting layer and the display structure.

Abstract: A thin film transistor substrate, a display apparatus using the same and a manufacturing method thereof are provided. The display apparatus includes a thin film transistor substrate, a top substrate and a display medium layer. The thin film transistor substrate includes a composite plate and several thin film transistors. The composite plate includes a core material structure and two insulation structures. The core material structure includes a metal layer. The two insulation structures are respectively disposed at two sides of the core material structure so as to sandwich the core material structure therebetween. The thin film transistors are disposed on the composite plate. The display medium layer is disposed between the thin film transistor substrate and the top substrate.

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

Abstract: A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

Abstract: A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.

Abstract: A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter.

Abstract: A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not.

Abstract: A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.