Patents by Inventor Chi Cheng

Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12162817
    Abstract: Improvements in catalyst systems and associated processes for the conversion of glycolaldehyde to monoethanolamine are disclosed. The catalyst systems exhibit improved selectivity to this desired product and consequently reduced selectivity to byproducts such as diethanolamine and ethylene glycol. These beneficial effects are achieved through the use of acids, and particularly Lewis acids, as co-catalysts of the reductive amination reaction, in conjunction with a hydrogenation catalyst.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 10, 2024
    Assignee: ARCHER-DANIELS-MIDLAND COMPANY
    Inventors: James Brazdil, Chi-Cheng Ma
  • Patent number: 12167525
    Abstract: An extreme ultra violet (EUV) radiation source apparatus includes a collector, a target droplet generator for generating a tin (Sn) droplet, a rotatable debris collection device and a chamber enclosing at least the collector and the rotatable debris collection device. The rotatable debris collection device includes a first end support, a second end support and a plurality of vanes, ends of which are supported by the first end support and the second end support, respectively. A surface of at least one of the plurality of vanes is coated by a catalytic layer, which reduces a SnH4 to Sn.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chieh Chien, Po-Chung Cheng, Chia-Chen Chen, Jen-Yang Chung, Li-Jui Chen, Tzung-Chi Fu, Shang-Ying Wu
  • Patent number: 12165975
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20240400182
    Abstract: The present disclosure is a forward-facing rowing mechanical device for on-water paddling transportation equipment. The device is comprised of a novel mechanism which re-diverts effort from legs of the rower to the opposite direction. Therefore, the water propelling direction is changed by the mechanism from backward driving to forward driving. The device includes a backbone; a seat on top of the backbone; a sliding rigger carrying oars; a foot plate for receiving effort from the rower; the effort diverting mechanism for changing driving direction and other necessary peripheral parts.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventor: Lok Chi Cheng
  • Publication number: 20240405081
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.
    Type: Application
    Filed: August 6, 2024
    Publication date: December 5, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Chi Cheng, Yu-Jen Huang, Shin-Hong Chen
  • Publication number: 20240405054
    Abstract: A monolithic array chip comprises a first semiconductor layer; a common electrode located on the first semiconductor layer; a first light-emitting unit with a first electrode located on the first semiconductor layer; a second light-emitting unit with a second electrode located on the first semiconductor layer; a third light-emitting unit with a third electrode located on the first semiconductor layer, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Inventors: Min-Hsun HSIEH, Chih-Ming WANG, Jan-Way CHIEN, Hui-Ching FENG, Yu-Chi WANG, Hsia-Ching CHENG
  • Publication number: 20240399906
    Abstract: A vehicle charging device includes a base, a circuit board, a plurality of supporting pillars and a plurality of conductors. The base has an accommodating space. The circuit board is located in the accommodating space. The plurality of supporting pillars are located in the accommodating space, and are connected to the base. Each of the plurality of conductors includes a contact portion and a connection portion. The plurality of contact portions are disposed on the base. The plurality of contact portions are located outside the accommodating space. The plurality of connection portions are connected to the plurality of contact portions, respectively. The plurality of connection portions penetrate through the base. The plurality of connection portions are partially located in the accommodating space. The plurality of connection portions are electrically connected to the circuit board.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 5, 2024
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Chi-Cheng HSIAO
  • Patent number: 12159598
    Abstract: An e-paper display apparatus includes an e-paper display panel including multiple source lines, multiple gate selection lines, and multiple pixel circuits and a driver circuit coupled to the e-paper display panel and configured to output a driving signal to the gate selection line. The gate selection lines and the source lines are disposed along a first direction. The source lines corresponding to the gate selection line simultaneously receive respective data signals when the gate selection line is turned on. The driving signal includes a first period and a second period. The gate selection line is turned on during the first period, and the gate selection line is turned off during the second period. A time length of the first period is greater than a time length of the second period.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: December 3, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Jia-Hung Chen, An-Chi Liu, Yu-Mao Lin, Kuang Cheng Fu, Pei Ju Wu
  • Patent number: 12159787
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12160013
    Abstract: A robot includes a limit device and an energy storehouse, the limiting device may lock or loosen a battery opened in the energy storehouse, the limiting device includes a first connecting member, a transmission rod, and a second connecting member. The first connecting member includes a first main body portion and two first connecting elements arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod includes a first end and a second end arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member includes two indexing buckles arranged at intervals, each of the indexing buckles includes a first limiting groove and a second limiting groove.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: December 3, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
  • Publication number: 20240395902
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Publication number: 20240395631
    Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Yi Chen HO, Yu-Chuan CHEN, Chieh CHENG, Chi-Hsun LIN, Zheng-Yang PAN, Shahaji B. MORE
  • Publication number: 20240395564
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The isolation layer includes fluorine, and a first concentration of fluorine in the isolation layer increases toward a top surface of the isolation layer. The semiconductor device structure includes a gate stack over the isolation layer and wrapping around the fin portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO
  • Patent number: 12150427
    Abstract: An intelligent defecation device for living creature includes a device body, a supporting portion, an image module, and a first analysis module. The supporting portion is formed within the inner side of the device body for accommodating a moisture absorption member so as to allow the living creature to leave over its excrement therein. The image module is also arranged at the device body for dynamically capturing the images of the excrement in the supporting portion and outputting the image. The first analysis module is arranged in the device body and connected with the image module to analyze and calculate the defecation mode with the image based on preset or accumulated data, so as to generate a signal when an abnormal defecation mode is diagnosed.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: November 26, 2024
    Assignee: LuluPet Co., Ltd.
    Inventors: James Cheng-Han Wu, Pei-Hsuan Shih, Chun-Ming Su, You-Gang Kuo, Ning-Yuan Lyu, Chi-Yeh Hsu, Liang-Hao Huang
  • Patent number: 12155928
    Abstract: A projection system and a method for selecting an image capturing number for image blending are provided. Multiple projection devices are driven one-by-one to project a pattern; multiple image capturing devices are driven to capture the pattern projected by each projection device, so as to obtain multiple image capturing results corresponding to the image capturing devices. Finally, at least one of the image capturing devices is selected to serve as an image capturing source for image blending based on the image capturing results. An image capturing range is identified through projected patterns, and an effective range is calculated and then selected for use, which is used for calculations required for automatic blending, so as to avoid a problem of being unable to maintain blending and merging due to environmental influences or failure of the image capturing device when performing image recognition and calculation required for automatic blending and merging.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 26, 2024
    Assignee: Coretronic Corporation
    Inventors: Chien-Chun Peng, Hsun-Cheng Tu, Chi-Wei Lin
  • Patent number: 12153346
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20240383333
    Abstract: A cockpit display system adapted to be installed in a cockpit and including a touch display, at least one head-up display, and a control unit. The touch display is disposed in a steering wheel in the cockpit and is adapted to display image information. A decorative layer of the steering wheel covers a display surface of the touch display. The at least one head-up display is adapted for display on a see-through window of the cockpit. The control unit is electrically connected to the touch display and the at least one head-up display. The control unit is adapted to display the image information on at least one of the touch display and the at least one head-up display according to a touch action performed on the touch display. Another cockpit display system is also provided.
    Type: Application
    Filed: December 20, 2023
    Publication date: November 21, 2024
    Applicant: AUO Corporation
    Inventors: Yu-Chi Chen, Chi-Yu Liu, Chia-Sheng Cheng
  • Publication number: 20240387173
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240385514
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Patent number: D1053815
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 10, 2024
    Assignee: SAMTEC, INC.
    Inventor: Chia Chi Cheng