Patents by Inventor Chi Cheng

Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12135501
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20240365003
    Abstract: An image capturing device comprising an image sensor and a processing circuit. The processing circuit is configured to perform following steps: (a) outputting first sensing frames by the image sensor in a first mode, wherein a first frame time duration is determined between adjacent ones of the first sensing frames; (b) switching from the first mode to a second mode in a transition time interval; (c) setting the transition time interval such that a difference between the transition time interval and the first frame duration is smaller than a predetermined value; and (d) outputting second sensing frames by the image sensor in the second mode.
    Type: Application
    Filed: April 29, 2024
    Publication date: October 31, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yan-Shao Liu, Yun-Feng Tseng, Chi-Cheng Ju
  • Publication number: 20240364825
    Abstract: A film clamping device includes a film holder formed in a flat shape, a cap and a plurality of limiting pads. One side of the film holder defines a first fixing slot vertically penetrating through the film holder. The first fixing slot accommodates a negative film. A dimension of the cap is disposed to be cooperated with a dimension of the first fixing slot so as to be fastened to the film holder. A bottom surface of the cap is provided as a flat surface. The plurality of the limiting pads are made of elastic materials. The plurality of the limiting pads are disposed around a peripheral wall of the first fixing slot.
    Type: Application
    Filed: March 5, 2024
    Publication date: October 31, 2024
    Inventors: Yun Long Lai, Chi Cheng Chuang
  • Publication number: 20240363676
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20240363539
    Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.
    Type: Application
    Filed: July 4, 2024
    Publication date: October 31, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Cheng Chen, Li-Hsuan Ho, Tsuo-Wen Lu, Shih-Hao Liang, Tsung-Hsun Wu, Po-Jen Chuang, Chi-Mao Hsu
  • Publication number: 20240360548
    Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Chi-Cheng HUNG, Pei-Wen WU, Yu-Sheng WANG, Pei-Shan CHANG
  • Publication number: 20240362470
    Abstract: The application provides a panoramic perception method, system and a non-transitory computer readable medium. The panoramic perception method comprises: performing a first pretraining on a plurality of weights of a training model using the source database; performing a second pretraining with data augmentation on the plurality of weights of the training model using the source database; performing a combined training on the plurality of weights of the training model using both the source database and the target database; performing a quantization-aware training on the plurality of weights of the training model using the source database and the target database; performing a post training quantization on the plurality of weights of the training model using the target database; and performing panoramic perception by the training model.
    Type: Application
    Filed: October 3, 2023
    Publication date: October 31, 2024
    Inventors: Yu-Chen LU, Sheng-Feng YU, Wei-Cheng LIN, Chi-Chih CHANG, Pei-Shuo WANG, Kuan-Cheng LIN, Kai-Chiang WU
  • Publication number: 20240363409
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Publication number: 20240353941
    Abstract: A display device includes an in-cell touch display panel, a flexible printed circuit board, and a source driver. The in-cell touch display panel includes touch sensing electrodes, touch sensing pins, pixel electrodes, and source pins. The touch sensing pins are electrically connected to the touch sensing electrodes. The source pins are electrically connected to the pixel electrodes. The flexible circuit board includes dummy pads, touch sensing leads, input pads, output pads, and output signal leads. The touch sensing leads are electrically connected to the dummy pads and the touch sensing pins. The output signal leads are electrically connected to the output pads and the source pins. The source driver includes input terminals and output terminals. The input terminals are electrically connected to the input pads. The output terminals are electrically connected to the output pads. The source driver does not include a touch sensing terminal.
    Type: Application
    Filed: December 15, 2023
    Publication date: October 24, 2024
    Inventors: Chi-Cheng CHEN, Chun-Fan CHUNG
  • Publication number: 20240351376
    Abstract: A tire structure, including a rim, an outer tire, an inner tube, and an inflating valve; an outer peripheral surface of the rim is provided with a mounting groove; tire beads of the outer tire are hermetically connected with side walls of the mounting groove, so that a hermetically sealed air cavity is formed between the rim and the outer tire; the inner tube is annular and made of an elastic porous material, with a sectional size larger than that of the air cavity; the inner tube is disposed in the air cavity so that an outer surface of the inner tube is tightly attached to an inner wall of the air cavity; the inflating valve is mounted to the rim to inflate the air cavity and the inner tube. Impact force can be absorbed to protect the rim even when the tire is not completely inflated.
    Type: Application
    Filed: December 11, 2023
    Publication date: October 24, 2024
    Inventor: PAI-CHI CHENG
  • Publication number: 20240355880
    Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Publication number: 20240355707
    Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Inventors: Yung-Chin HOU, Li-Chun TIEN, Chih-LIang CHEN, Chi-Yu LU, Wei-Cheng LIN, Guo-Huei WU
  • Publication number: 20240355623
    Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chen KUO, Chih-Cheng LIU, Ming-Hui WENG, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Patent number: 12122739
    Abstract: An integrated, co-product capable process is provided for producing taurine in particular with optionally one or both of monoethanolamine and diethanolamine from one or more sugars, comprising pyrolyzing one or more sugars to produce a crude pyrolysis product mixture including glycolaldehyde and formaldehyde; optionally removing formaldehyde from the crude pyrolysis product mixture, then combining the crude pyrolysis product mixture with an aminating agent in the presence of hydrogen and further in the presence of a catalyst to produce at least monoethanolamine from the crude pyrolysis product mixture; optionally recovering diethanolamine from the crude reductive amination product, sulfating at least a portion to all of the monoethanolamine product to produce 2-aminoethyl hydrogen sulfate ester; and sulfonating the 2-aminoethyl hydrogen sulfate ester to produce taurine.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 22, 2024
    Assignee: ARCHER-DANIELS-MIDLAND COMPANY
    Inventors: James Brazdil, Chi-Cheng Ma
  • Patent number: 12124178
    Abstract: A system is provided. The system includes an exposing device configured to generate a real-time image, including multiple first align marks, of a mask and an adjusting device configured to adjust an off-set of the mask from a pre-determined position to be smaller than a minimum aligning distance according to the first align marks and multiple align marks on a substrate, and further to move the mask closer to the pre-determined position to have a displacement, less than a minimum mapping distance, from the pre-determined position according to the real-time image and a reference image of the mask.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Yu Lan, Po-Chung Cheng, Ching-Juinn Huang, Tzung-Chi Fu, Tsung-Yen Lee
  • Publication number: 20240346624
    Abstract: An asymmetric image fusion method is applied to an operation device and includes acquiring a first image stream with a first frame rate, acquiring a second image stream with a second frame rate different from the first frame rate, and fusing a first reused image frame of the first image stream with a set of second image frames of the second image stream respectively for outputting a set of fused image frames.
    Type: Application
    Filed: April 17, 2024
    Publication date: October 17, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chi-Cheng Ju, Ying-Jui Chen, Jing-Ying Chang, Shan-Lung Chao
  • Publication number: 20240343329
    Abstract: An electronically controlled bicycle kickstand lock has an electronic controller, a fixing member, a kickstand resisting member, and a kickstand. The fixing member can be moved or rotated under the control of the electronic controller. The kickstand resisting member can move or rotate and abuts the fixing member. The kickstand can rotate and selectively abuts the kickstand resisting member. When the fixing member is in the locked state, the lowered kickstand is limited by the kickstand resisting member and cannot be kicked up. Therefore, the kickstand will always be in the flip-down state, so that the kickstand is not only convenient to ride, but also tends to lean against the ground when turning. There is no need to use or carry an independent lock, only through various ways to control the electronic controller, making the kickstand able or unable to be kicked up.
    Type: Application
    Filed: April 10, 2024
    Publication date: October 17, 2024
    Inventors: Chia-Wei WENG, Yueh-Cheng HUANG, Hao-Jhong LYU, Chi-Liang LIEN
  • Publication number: 20240347118
    Abstract: A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.
    Type: Application
    Filed: May 18, 2023
    Publication date: October 17, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Lung-Chi Cheng, Shan-Hsuan Tsai, Ying-Shan Kuo, Ngatik Cheung, Ju-Chieh Cheng
  • Publication number: 20240347360
    Abstract: A wafer storage device is provided. The wafer storage device includes a floor, a ceiling, and one or more walls between the floor and the ceiling to define a wafer storage chamber for storage of one or more wafers. The apparatus includes a particle-attraction object, having a positive charge or a negative charge, in the wafer storage chamber and configured to attract particles in the wafer storage chamber.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Yuan-Cheng KUO, Chi-Chung JEN, Kai-Hung HSIAO, Pei-Huang HSU, Chih-Hsiung HUANG
  • Patent number: 12120472
    Abstract: Various schemes pertaining to generating a full-frame color image using a hybrid sensor are described. An apparatus receives sensor data from the hybrid sensor, wherein the sensor data includes partial-frame chromatic data of a plurality of chromatic channels and partial-frame color-insensitive data. The apparatus subsequently generates full-frame color-insensitive data based on the partial-frame color-insensitive data. The apparatus subsequently generates the full-frame color image based on the full-frame color-insensitive data and the partial-frame chromatic data. The apparatus provides benefits of enhancing image quality of the full-frame color image especially under low light conditions.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: October 15, 2024
    Inventors: Yu-Ju Lin, Ying-Jui Chen, Keh-Tsong Li, Pin-Chung Lin, Hung-Chih Ko, Chi-Cheng Ju