Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: An electronic device includes a housing and a first heat source, a second heat source, and a heat dissipation module that are disposed in the housing. The heat dissipation module includes a first fan, a second fan, a first heat conduction member, and a second heat conduction member. The first fan and the second fan are disposed on two opposite sides of the housing. One end of the first heat conduction member is disposed at the first fan, and the other end is located at a position on a side of an upper surface of the housing corresponding to the first heat source. One end of the second heat conduction member is disposed at the second fan, and the other end is located on a side of a lower surface of the housing and abuts against the second heat source.

Abstract: Systems and techniques are described for performing foveated sensing. In some aspects, a method (e.g., implemented by an image sensor) can include capturing sensor data for a frame associated with a scene, obtaining information corresponding to a region of interest (ROI) associated with the scene, generating a first portion (having a first resolution) of the frame corresponding to the ROI, generating a second portion of the frame having a second resolution, and outputting (e.g., to an image signal processor (ISP)) the first portion and the second portion. In some aspects, a method (e.g., implemented by an ISP) can receive, from an image sensor, sensor data for a frame associated with a scene, generating a first version (having a first resolution) of the frame based on an ROI associated with the scene, and generating a second version of the frame having a second resolution (lower than the first resolution).

Abstract: A conductive terminal is suitable for being installed in a terminal receiving slot of a base, and includes a main body, an elastic arm portion and a foot connecting portion. The main body includes a holding portion and a buckle portion. The elastic arm portion includes a reversed folded portion, an abutment portion, a bending portion and a conductive portion. The reversed folded portion extends downward from a lower surface of the main body and extends upward after being folded. The abutment portion is opposite to the main body, and located between the reversed folded portion and the bending portion. The bending portion is connected to the abutment portion and the conductive portion. The foot connecting portion is connected to the main body or the reversed folded portion, and provided with a ball soldering member for connecting to soldering balls.

Abstract: An improved process and catalyst are provided for making an FDCA diester monomer product with improved productivity compared to an autocatalyzed esterification but with comparable or at least not greatly diminished color properties compared to the FDCA diester monomer product that would be produced autocatalytically, wherein a heterogeneous tin (II) catalyst is employed to make an esterification product comprising a diester of FDCA with an alcohol, the catalyst being in either a bulk, unsupported form or in the form of a supported tin (II) catalyst, in particular, using a hygroscopic support such as a gamma alumina, a zeolite or a silica, or using a carbon support.

Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier substrate; forming a first base layer on the carrier substrate; forming a working unit on the first base layer, performing a detection step on the working unit to identify whether a defect is present, wherein the detection step includes automated optical inspection (AOI), electrical detection, or a combination thereof; and repairing the electronic device.

Abstract: The drilling system withstands downhole conditions at the bottom of the borehole and drilling conditions due to the constant movement and vibration. The drilling system includes a drill bit and a sensor system with a system housing, a primary power supply and interior sensor. The primary power supply includes piezoelectric panels for converting radial vibration into energy. The interior sensor is locally powered by the primary power supply at the remote downhole location at the bottom of the borehole. The interior sensor collects data related to a downhole condition and is in communication with the primary power supply to generate confirmed data based on the amount of energy generated by the primary power supply. The confirmed data is more accurate and reliable than the data collected by the interior sensor and can be used to guide the path of the drill bit through the rock formation in drilling operations.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: The drilling system withstands downhole conditions at the bottom of the borehole and drilling conditions due to the constant movement and vibration. The drilling system includes a drill bit and a sensor system with a system housing, a primary power supply and interior sensor. The primary power supply includes piezoelectric panels for converting radial vibration into energy. The interior sensor is locally powered by the primary power supply at the remote downhole location at the bottom of the borehole. The interior sensor collects data related to a downhole condition and is in communication with the primary power supply to generate confirmed data based on the amount of energy generated by the primary power supply. The confirmed data is more accurate and reliable than the data collected by the interior sensor and can be used to guide the path of the drill bit through the rock formation in drilling operations.

Abstract: A hybrid power system including a transmission module, a motor, an engine generator, an energy storage module, and an electrical energy distributor is disclosed. The motor is connected to the transmission module. The electrical energy distributor is coupled to the motor. The engine generator is coupled to the electrical energy distributor. The engine generator is adapted to rotate at a constant speed to generate a first power, and the first power is transmitted to the motor and the energy storage module by the electrical energy distributor.

Abstract: An image sensor includes an array of image pixels and black level correction (BLC) pixels. Each BLC pixel includes a BLC pixel photodetector, a BLC pixel sensing circuit, and a BLC pixel optics assembly configured to block light that impinges onto the BLC pixel photodetector. Each BLC pixel optics assembly may include a first portion of a layer stack including a vertically alternating sequence of first material layers having a first refractive index and second material layers having a second refractive index. Additionally or alternatively, each BLC pixel optics assembly may include a first portion of a layer stack including at least two metal layers, each having a respective wavelength sub-range having a greater reflectivity than another metal layer. Alternatively or additionally, each BLC pixel optics assembly may include an infrared blocking material layer that provides a higher absorption coefficient than color filter materials within image pixel optics assemblies.

Abstract: Provided are semiconductor dies and methods for manufacturing semiconductor devices on a die. A method for manufacturing semiconductor devices on a die includes forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm).

Abstract: An electronic component includes a first electronic unit including a plurality of pads, a first conductive layer, a second conductive layer, a first insulating layer having a first thickness, a second insulating layer having a second thickness, a second electronic unit, and a solder ball. The first conductive layer is disposed between the first electronic unit and the second conductive layer, and electrically connected to at least one of the pads through a conductive via. The first insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed between the first insulating layer and the second insulating layer. The first thickness is different from the second thickness. The second conductive layer is disposed between the first conductive layer and the second electronic unit. The second conductive layer is electrically connected to the second electronic unit through the solder ball.

Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Abstract: An electrochromic rearview mirror assembly comprises a first substrate, a second substrate, an electrochromic medium, a light-transmitting conductive layer, a transflective film and a hiding perimeter layer. The first substrate includes a first surface and a second surface. The first surface comprises a first peripheral region and a first primary region. The second surface comprises a second peripheral region and a second primary region. The second substrate comprises a third surface and a fourth surface. The electrochromic medium is disposed between the first substrate and the second substrate. The light-transmitting conductive layer is disposed on the second primary region of the second surface. The transflective film is disposed on the third surface of the second substrate. The hiding perimeter layer is disposed on the second peripheral region of the second surface.