Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Abstract: A device includes a semiconductor fin, an isolation layer, a dielectric fin structure, and a gate structure. The semiconductor fin is over a substrate. The isolation layer is over the substrate and adjacent the semiconductor fin. The dielectric fin structure is over the isolation layer and includes a bottom dielectric fin and a top dielectric fin. The isolation layer surrounds a bottom of the bottom dielectric fin. The top dielectric fin is over the bottom dielectric fin and is spaced apart from the isolation layer. The gate structure is across the semiconductor fin and the dielectric fin structure, wherein a portion of the gate structure in contact with the isolation layer has a first width, and another portion of the gate structure in contact with the top dielectric fin has a second width greater than the first width.

Abstract: A host system coupled to a storage system provides hardware support for command abort. The host system includes a host controller, which detects that a host driver has disabled an enable indicator of a submission queue (SQ). In response to the detection, the host controller stops further fetching from the SQ. The host controller sends all entries that have been fetched from the SQ to the storage device, and sets a status indicator of the SQ to indicate stopped fetching of the SQ.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

Abstract: An extraction cleaner may include a base, an upright body pivotally coupled to the base, a supply tank removably coupled to the upright body and a recovery tank removably coupled to the upright body. The base may include a non-removable door and a removable suction nozzle. At least one fluid dispensing nozzle may be provided on the door. The door may be pivotally coupled to the base for providing access to an agitator. The cleaner may include and auto-spray configuration. The cleaner may include a support on the upright portion for the recovery tank. The cleaner may include an additive tank received in a receptacle of the supply tank. The recovery tank may include a float and/or an airflow management configuration. The cleaner may include a cleaning tool and a suction changeover valve and/or a fluid changeover valve. The cleaner may include a mixing valve for supplying fluid to a fluid changeover valve.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: This invention provides herbal compositions useful for increasing the therapeutic index of chemotherapeutic compounds. This invention also provides methods useful for improving the quality of life of an individual undergoing chemotherapy. Furthermore, this invention improves the treatment of disease by increasing the therapeutic index of chemotherapy drugs by administering the herbal composition PHY906 to a mammal undergoing such chemotherapy.

Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.

Abstract: An erasing method of a memory device includes the following steps. It is determined whether a memory passes the first erasing verification operation according to the first erasing verification threshold. When the memory does not pass the first erasing verification operation, an erasing operation is performed on the memory. When the memory passes the first erasing verification operation, a flag is generated and it is determined whether the memory passes a second erasing verification operation according to the second erasing verification threshold. When the memory does not pass the second erasing verification operation, the erasing operation is performed on the memory. When the memory passes the second erasing verification operation, an over-erase correction is performed on the memory. It is determined whether there is a flag indicating that all addresses pass the first erasing verification to determine whether the memory passes the first or second erasing verification operation.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

Abstract: An optical filter system is provided. The system includes a first collimator, a second collimator, and a reflective optical filter. An optical signal is inputted through a first port of the first collimator, is outputted through a second port of the first collimator, is filtered by the reflective optical filter, the filtered optical signal is inputted through second port of the first collimator and outputted through first port of the first collimator. The optical signal is inputted through a first port of the second collimator, is outputted through a second port of the second collimator, is filtered by the reflective optical filter, the filtered optical signal is inputted through the second port of the second collimator and outputted through the first port of the second collimator. The optical signal outputted through the first port of the first collimator is inputted to the first port of the second collimator.

Abstract: The invention provides an optical coherence tomography self-testing system, an optical coherence tomography method and an ocular disease monitoring system. The optical coherence tomography self-testing system comprises a camera device, an external display module and a communication module. The camera device includes an image-capturing module and a processing module. The image-capturing module captures a plurality of ocular images. The processing module is connected to the image-capturing module, and the processing module determines whether a position offset value between the pupil center position of a tested eyeball and an optical axis of the image-capturing module is within a preset error range. If the position offset value is within the preset error range, the plurality of ocular images is stored as a plurality of displayed images. The external display module displays one of the plurality of displayed images and a status light after the image-capturing module has completed image capturing.

Abstract: The present invention relates to capsules comprising dasatinib lauryl sulfate salt.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.