Patents by Inventor Chi-Cheng Hung
Chi-Cheng Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363409Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
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Publication number: 20240360548Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Chi-Cheng HUNG, Pei-Wen WU, Yu-Sheng WANG, Pei-Shan CHANG
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Publication number: 20240332374Abstract: A method and structure for forming semiconductor device includes forming a first opening in a dielectric layer to expose a source/drain region. In some embodiments, the method further includes depositing a first metal layer in the opening and over the source/drain region. Thereafter, in some examples, the method further includes performing an annealing process to modulate a grain size of the first metal layer. In various embodiments, the method further includes depositing a second metal layer over the annealed first metal layer. In some embodiments, the second metal layer has a substantially uniform phase.Type: ApplicationFiled: October 23, 2023Publication date: October 3, 2024Inventors: Chi-Cheng HUNG, Pei-Wen WU, Pei Shan CHANG
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Publication number: 20240304725Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: ApplicationFiled: May 21, 2024Publication date: September 12, 2024Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Patent number: 12065731Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.Type: GrantFiled: January 21, 2021Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Cheng Hung, Pei-Wen Wu, Yu-Sheng Wang, Pei-Shan Chang
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Patent number: 12068197Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.Type: GrantFiled: April 19, 2021Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
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Publication number: 20240249977Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.Type: ApplicationFiled: February 21, 2024Publication date: July 25, 2024Inventors: Pei-Wen WU, Chun-I TSAI, Chi-Cheng HUNG, Jyh-Cherng SHEU, Yu-Sheng WANG, Ming-Hsing TSAI
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Patent number: 12021147Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: GrantFiled: December 12, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Patent number: 11955379Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.Type: GrantFiled: September 15, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
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Patent number: 11901188Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: GrantFiled: March 28, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Publication number: 20230268402Abstract: A semiconductor device includes a source/drain region, a silicide region, a source/drain contact, and a silicon-containing dielectric liner. The source/drain region is in a substrate. The silicide region is embedded in the source/drain region. The source/drain contact is over the silicide region. The silicon-containing dielectric liner surrounds the source/drain contact. The source/drain region is in contact with an outer sidewall of the silicon-containing dielectric liner but separated from a bottom surface of the silicon-containing dielectric liner by the silicide region.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Cheng HUNG, Kei-Wei CHEN, Yu-Sheng WANG, Ming-Ching CHUNG, Chia-Yang WU
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Patent number: 11670690Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.Type: GrantFiled: July 11, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Cheng Hung, Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching Chung, Chia-Yang Wu
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Publication number: 20230107945Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Patent number: 11616132Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.Type: GrantFiled: June 7, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su
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Patent number: 11563120Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: GrantFiled: October 22, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Publication number: 20220228257Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.Type: ApplicationFiled: January 21, 2021Publication date: July 21, 2022Inventors: Chi-Cheng HUNG, Pei-Wen WU, Yu-Sheng WANG, Pei-Shan CHANG
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Publication number: 20220223428Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Patent number: 11355040Abstract: A method for inspecting functionality of a display device and a test equipment are provided. The method for inspecting functionality of the display device is utilized in a test equipment of an auto-test system. The method includes controlling an image capturing device to capture a test image shown on a screen of the display device for generating a captured image, acquiring an encoded pattern from the captured image and decoding the encoded pattern, wherein the test image is a source image generated by an image providing device superposed with the encoded pattern, determining whether the encoded pattern is successfully decoded to generate a resultant data, and comparing the resultant data with reference data to generate a comparison result after the encoded pattern is successfully decoded, wherein the reference data comprises information associated with the test image and information associated with system configuration of the display device.Type: GrantFiled: November 11, 2020Date of Patent: June 7, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Sheng-Nan Sun, Jia-yu Wang, Chi-Cheng Hung, Kun-Yen Wu
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Publication number: 20220148469Abstract: A method for inspecting functionality of a display device and a test equipment are provided. The method for inspecting functionality of the display device is utilized in a test equipment of an auto-test system. The method includes controlling an image capturing device to capture a test image shown on a screen of the display device for generating a captured image, acquiring an encoded pattern from the captured image and decoding the encoded pattern, wherein the test image is a source image generated by an image providing device superposed with the encoded pattern, determining whether the encoded pattern is successfully decoded to generate a resultant data, and comparing the resultant data with reference data to generate a comparison result after the encoded pattern is successfully decoded, wherein the reference data comprises information associated with the test image and information associated with system configuration of the display device.Type: ApplicationFiled: November 11, 2020Publication date: May 12, 2022Inventors: Sheng-Nan Sun, Jia-yu Wang, Chi-Cheng Hung, Kun-Yen Wu
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Patent number: 11289338Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: GrantFiled: July 9, 2020Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen