Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A multi-memory collaboration structure based on SPI interface is provided, including a first memory, a second memory, and a control module. In an embodiment, instruction codes of first actuating commands transmitted from the control module to the first memory are different from those of second actuating commands transmitted from the control module to the second memory. In another embodiment, a first actuating command has a preselected instruction code and an alternate instruction code, and a second actuating command has a second instruction code, wherein the preselected instruction code is different from the alternate instruction code, and at least one of the preselected instruction code and the alternate instruction code is different from the second instruction code. Therefore, the invention only requires one chip select port to avoid signal conflict between different memories, thereby effectively reducing the fabrication costs.

Abstract: Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.

Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.

Abstract: A dual-chip package structure is provided with an exposed pad as a ground terminal for being electrically coupled to GND bonding pads of two chips in the package structure. A leadframe of the package structure is provided with two CS (chip select) pins electrically coupled to CS bonding pads of the two chips respectively, so as to avoid conflict between the two chips on the premise that the package structure only has eight pins. Thereby, the invention provides a dual-chip package structure with low pin count, which can effectively reduce its cost.

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof.

Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.