Abstract: A semiconductor varactor with reduced parasitic resistance is disclosed. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) in a further embodiment to reduce the parasitic resistance.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layers (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well region (30) in a common substrate region.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: Bipolar transistor performance is improved in CMOS process with deep wells by increasing the relative doping density between the emitter and base. To do this, the base dopant concentration is decreased in an npn device by using only the starting p substrate or epitaxial material, and NOT the p-well implant, to form the base*.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well region (30) in a common substrate region.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.

Abstract: A computer image display device includes a light transparent glass anode plate (10) spaced from a cathode substrate (12) which has a plurality of microtips (14). Plate (10) has an inside surface (25) which is contoured with an array of prisms (36) having equal sides (58, 59) that converge rearwardly toward apexes (38) of peaks (36). Apexes (38) are covered with light absorbing material (47), then covered at anode comb forming regions (51, 52, 53) with conductive material (48). Different color luminescing phosphors (24a, 24b, 24c) are applied over the respective anode combs (51, 52, 53). Sides (58, 59) direct ambient light toward apexes (38) for absorption by material (47). Light emitted by phosphors (24a, 24b, 24c) is directed by valleys (60) toward outside surface (35) of plate (10).

Abstract: A grooved anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B. In one embodiment, grooves 50, having generally straight sidewalls, are formed in the upper surface of planar substrate 42 at the interstices of conductors 46. In a second embodiment, grooves 50', which provide a substantial undercutting of the material of substrate 42' adjacent the edges of conductors 46', are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. A substantially opaque, electrically insulating material 52 is affixed to substrate 42 in the grooves 50 formed between conductors 46, acting as a barrier to the passage of ambient light into and out of the device.

Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). Apertures (26) are arranged in regular, periodic arrays (23, 23', 123, 123') defining lattices having occupied apertured positions and internal unapertured vacancy positions (150, 150'). The insulating spacer (125) is etched to undercut electrode (22) to connect apertured lattice positions, forming a common cavity (141) for microtips (14) within each mesh spacing (16), and leaving central posts (143) at the unapertured vacancies (150, 150'). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.

Abstract: An electron emitter plate (10, 10') for an FED image display has a gate conductive layer (22) spaced by a dielectric insulating layer (25) from a cathode conductive layer formed into a mesh (18). Arrays (12) of microtips (14) are located within mesh spacings (16) for field emission of electrons toward a phosphor layer (34) of an anode plate (11). Cathode layer (18) is patterned into column stripes (19) separated by gaps (17). Gate layer (22) is patterned into row cross-stripes (24) separated by gaps (23) which intersect with stripes (19) at matrix addressable pixel locations (30). Resistive layer (15) is patterned into stripes (40) separated by gaps (42) which interrupt column-to-column electrical communication through resistive layer (15). Unetched strips (43) are provided to bridge gap discontinuities for deposition of gate layer (22) at crossovers of rows (24) between columns (19).

Abstract: A glass heating and sealing system (10, 30, 60) and method for manufacturing a flat panel display including anode and cathode glass panels with a vacuum compartment between them includes a plurality of vacuum chambers (12, 14, 16, 18, 20, 32, 34, 36, 38, 61, 76) for processing glass panels (39, 63, 74). Transfer of glass panels (39, 63, 74) between chambers (12, 14, 16, 18, 20, 32, 34, 36, 38, 61, 76) is accomplished by a transfer mechanism (24, 42, 68, 72) located within a central vacuum chamber (22, 40, 70) commonly connected to the other chambers. System (10, 30, 60) may include a rapid thermal processing (RTP) chamber (14, 34, 38, 76) for quick and even heating of the panels (39, 63, 74). System (10) includes an e-beam bombardment chamber (16) for preconditioning the anode glass panels, and a heating chamber (18) for fusing anode glass panels to cathode glass panels. Different levels of vacuum may be established in different chambers.

Abstract: A method of fabricating an anode plate 18 for use in a field emission device comprises the steps of providing a transparent substrate 20 and depositing a layer of a transparent, electrically conductive material 24 on a surface of the substrate. Next, portions of the layer of conductive material 24 are removed to form regions of the conductive material. Luminescent material 26 is then applied on the conductive regions and an outer portion 27 of at least some of the particles of the luminescent material are thereafter removed.

Abstract: A monolithic integrated circuit capable of operation in the microwave range which is fabricated using silicon technology wherein transmission line interconnects are fabricated along with active devices on the same substrate. The transmission line is provided using polycrystalline silicon since it can have much higher resistivity than single crystal silicon. Accordingly, a circuit is provided wherein active devices are provided in single crystal silicon and interconnects are formed overlying polycrystalline silicon to provide transmission line interconnects between devices and obtain the desired high frequency response.

Abstract: A computer image display device includes a light transparent glass anode plate (10) spaced from a cathode substrate (12) which has a plurality of microtips (14). Plate (10) has an inside surface (25) which is contoured with an array of prisms (36) having equal sides (58, 59) that converge rearwardly toward apexes (38) of peaks (36). Apexes (38) are covered with light absorbing material (47), then covered at anode comb forming regions (51, 52, 53) with conductive material (48). Different color luminescing phosphors (24a, 24b, 24c) are applied over the respective anode combs (51, 52, 53). Sides (58, 59) direct ambient light toward apexes (38) for absorption by material (47). Light emitted by phosphors (24a, 24b, 24c) is directed by valleys (60) toward outside surface (35) of plate (10).

Abstract: An mode plate 80 for use in a field emission flat panel display device comprises a transparent planar substrate 88 having a plurality of electrically conductive, parallel stripes 50 comprising the anode electrode of the device, which are covered by phosphors 84.sub.R, 84.sub.G and 84.sub.B. The conductors 50 which are covered by the same color phosphors are electrically interconnected by buses 52, 54, and 56. A substantially opaque, electrically insulating material 86 is affixed to substrate 88 in the spaces between conductors 50, acting as a barrier to the passage of ambient light into and out of the device. In addition, the same substantially opaque, electrically insulating material 86 is formed between the conductors 50 and the buses 52, 54, and 56, thereby providing electrical isolation between the two layers.