SEMICONDUCTOR VARACTOR WITH REDUCED PARASITIC RESISTANCE
A semiconductor varactor with reduced parasitic resistance is disclosed. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) in a further embodiment to reduce the parasitic resistance.
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This is a division of application Ser. No. 11/395,385, filed Mar. 31, 2006; which is a division of application Ser. No. 09/994,421, filed Nov. 27, 2001, which claims the benefit of provisional Application No. 60/253,620, filed Nov. 28, 2000.
BACKGROUNDThe invention relates to an integrated circuit including a metal oxide semiconductor varactor formed using CMOS technology.
In mixed signal applications it is sometimes necessary to have varactors as a part of the CMOS integrated circuit. A varactor is a capacitor whose capacitance value depends on the voltage applied to the capacitor. Typical integrated circuit varactors comprise metal oxide semiconductor (MOS) structures. The capacitor in a MOS structure is formed by the gate electrode (or gate), the gate dielectric layer and the semiconductor substrate. The gate will form one terminal of the capacitor and the semiconductor substrate will form the other terminal. Voltage applied across the gate and the semiconductor substrate will change the value of the capacitor. An important property of a MOS varactor is the ratio of the maximum capacitance of the varactor to the minimum value of capacitance or VR=Cmax/Cmin. Here Cmax represents the maximum varactor capacitance, Cmin the minimum varactor capacitance, and VR the varactor capacitance ratio. A number of factors will affect VR including gate dielectric thickness, substrate doping, gate electrode doping, series resistance, and frequency of operation. A number of these factors such as gate dielectric thickness, substrate doping, and gate electrode doping also affect the MOS transistors which comprise the integrated circuit and cannot be varied to maximize the capacitance ratio VR. Given the constraint imposed by the other devices comprising the integrated circuit, a way is needed to provide the circuit having increased varactor capacitance ratio VR without affecting the other integrated circuit devices present.
SUMMARY OF INVENTIONThe invention provides an integrated circuit including a semiconductor varactor with reduced parasitic resistance.
In a described embodiment, a contact isolation structure is formed in a well region. The contacts to the gate layer of the semiconductor are formed over the contact isolation structure thereby reducing the parasitic resistance of the semiconductor structure. This reduction in parasitic resistance results in an increase in the capacitance ratio of the structure compared to the prior art. In another embodiment of the invention, the gate contact is formed over the well region of the semiconductor structure.
For a more complete understanding of the invention and the advantages thereof, reference is now made to the following description of example embodiments taken in conjunction with the accompanying drawings, wherein:
Illustrated in
Following the formation of the gate dielectric layer 40, a gate electrode layer (or gate layer) 50 is formed over the gate dielectric layer 40. This gate layer is a conductive layer and usually comprises doped polycrystalline silicon or doped amorphous silicon. In some instances, a silicide layer will be formed on the gate layer 50. Following the formation of the gate layer 50, the heavily doped contact regions 35 are formed. These contact regions 35 are formed by implanting additional n-type dopants into n-well region 20. These heavily doped contact regions 35 will be used to contact the n-well region which will form one terminal of the varactor. In typical CMOS processes, these heavily doped contact regions will be formed using the source and drain region implantation process and the source and drain extension region implantation process. The structure shown in
Shown in
Following the formation of the varactor structure, contact structures 70 are formed to contact the gate layer 50. In forming the contact structures 70, a PMD layer is formed over the entire varactor structure. As described above, contact holes are formed in the PMD layer and conductive plugs are used to fill the contact holes to contact the gate layer 50. As illustrated in
In normal operation, the substrate surface of the active regions of the varactor 60 and 65 will change state depending on the voltage difference applied between the gate layer 50 and the heavily doped contact region 35. Depending on the substrate doping type (i.e., n-type or p-type) and voltage applied, the substrate surface in the active regions 60 and 65 will be either in a depletion state, an accumulation state, or an inversion state. The active region of the varactor can therefore be defined as that region of the substrate (or well region) where a substantial portion of the depletion region, accumulation region, or inversion region exists.
Shown in
Following the formation of the varactor structure, a contiguous PMD layer 130 is formed above the gate layers 110 and the contact regions 120. Contact holes are formed in the PMD layer and a conducting material(usually tungsten, aluminum, titanium, copper, or other suitable metal or alloy) is used to fill the contact holes to provide gate layer contacts 140 (or electrical contacts) and contact region contacts 170. In an embodiment, the gate layer contacts 140 are formed over the active regions 142 of the varactor. Forming the gate layer contacts 140 over the active regions 142 (and thus over the n-well region) reduces the parasitic resistance associated with the varactor and therefore increases the capacitance ratio VR. In a further embodiment, the gate layer contacts can be formed over isolation regions and not over active regions of the device structure. This will apply to the structures shown in
Shown in
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the claims encompass any such modifications or embodiments.
Claims
1. An integrated circuit including a varactor, comprising:
- a semiconductor substrate with at least a first isolation region and a second isolation region separated by a first distance;
- a well region of a first conductivity type formed in said semiconductor substrate between said first isolation region and said second isolation region;
- at least a first and a second active region defined in said well region by a contact isolation structure formed in said well region between said first isolation region and said second isolation region;
- contact regions of the first conductivity type formed in the first and second active regions;
- a gate dielectric layer formed on said first active region and said second active region;
- a gate electrode layer formed on said gate dielectric layer, wherein said gate electrode layer overlies said first active region, said second active region, and said contact isolation structure; and
- electrical contacts to said gate electrode layer, wherein said electrical contacts are formed over said contact isolation region.
2. The integrated circuit of claim 1, wherein said first and second isolation regions comprise shallow trench isolation (STI) structures.
3. The integrated circuit of claim 1, wherein said contact isolation structure comprises a shallow trench isolation (STI) structure.
4. An integrated circuit including a varactor, comprising
- a well region of a first conductivity type formed in a semiconductor;
- a gate dielectric layer formed on said well region;
- a gate electrode layer formed on said gate dielectric layer;
- contact regions of the first conductivity type formed in said well region, wherein said contact regions are source/drain implantations; and
- electrical contacts to said gate electrode layer, wherein said electrical contacts overlie a contact isolation structure formed in said well region.
5. The integrated circuit of claim 4, further comprising sidewall structures formed adjacent to said gate electrode layer.
6. The integrated circuit of claim 5, wherein said first conductivity type is n-type conductivity.
7. The integrated circuit of claim 6, wherein said first conductivity type is p-type conductivity.
8. The integrated circuit of claim 4, wherein said contact isolation structure comprises a shallow trench isolation (STI) structure.
Type: Application
Filed: Jun 8, 2010
Publication Date: Sep 30, 2010
Applicant: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventors: Kamel Benaissa (Garland, TX), Chi-Cheong Shen (Richardson, TX)
Application Number: 12/796,206
International Classification: H01L 29/78 (20060101);