Patents by Inventor Chi Ching

Chi Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150266825
    Abstract: Indazole compounds for treating various diseases and pathologies are disclosed. More particularly, the present disclosure concerns the use of an indazole compound or analogs thereof, in the treatment of disorders characterized by the activation of Wnt pathway signaling (e.g., cancer, abnormal cellular proliferation, angiogenesis, Alzheimer's disease, lung disease, fibrotic disorders, cartilage (chondral) defects, and osteoarthritis), the modulation of cellular events mediated by Wnt pathway signaling, and neurological conditions/disorders/diseases linked to overexpression of DYRK1A.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 24, 2015
    Inventors: John Hood, Sunil Kumar KC, David Mark Wallace, Gopi Kumar Mittapalli, Brian Joseph Hofilena, Chi Ching Mak, Venkataiah Bollu, Brian Eastman
  • Patent number: 9102674
    Abstract: The invention provides a chemical entity of Formula (I) wherein R1, R2, R3, Y, and n have any of the values described herein and compositions comprising such chemical entities; methods of making them; and their use in a wide range of methods, including metabolic and reaction kinetic studies, detection and imaging techniques, and radioactive treatments; and therapies, including inhibiting MAO, and MAO-B selectively, enhancing neuronal plasticity, treating neurological disorders, providing neuroprotection, treating a cognitive impairment associated with a CNS disorder, enhancing the efficiency of cognitive and motor training, providing neurorecovery and neurorehabilitation, enhancing the efficiency of non-human animal training protocols, and treating peripheral disorders (including obesity, diabetes, and cardiometabolic disorders) and their associated co-morbidities.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 11, 2015
    Assignee: Dart NeuroScience (Cayman) Ltd.
    Inventors: Jillian Basinger, Graeme Freestone, Varsha Gupta, Alan Kaplan, Chi-Ching Mak, Benjamin Pratt, Vincent Santora, Dipanjan Sengupta, Lino Valdez
  • Publication number: 20150187603
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Application
    Filed: March 10, 2015
    Publication date: July 2, 2015
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Publication number: 20150144384
    Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
    Type: Application
    Filed: December 12, 2013
    Publication date: May 28, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Chi-Ching Ho, Ying Chou Tsai, Sheng-Che Huang
  • Patent number: 9029433
    Abstract: A photocurable adhesive composition is provided, which comprises: a) a (meth)acrylate oligomer having one or more functional groups, b) a mono-functional monomer, a multi-functional monomer, or a mixture thereof, c) a photoinitiator, and d) a plasticizer having a refractive index of no less than 1.48. The photocurable adhesive composition of the present invention has good light transmittance, high refractive index and appropriate flowability and softness, and is easy to be coated and adhered. The photocurable adhesive composition of the present invention can be applied to optical products and simplify the manufacture processes, and provide adhesion property while retaining good reworkability and optical properties.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 12, 2015
    Assignee: Eternal Materials Co., Ltd.
    Inventors: Chi-Yu Huang, Chi-Ching Lu, Hsiun-Chia Shih
  • Publication number: 20150119285
    Abstract: A magnetic-assisted rapid aptamer selection (MARAS) protocol for screening DNA aptamer is proposed. The MARAS protocol is able to efficiently generate aptamers with high affinity and specificity. A rotating magnetic field or alternating magnetic field was used in combination with target-bound magnetic micro-particles or nanoparticles to select DNA aptamers having desirable affinity and specificity to the target.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Chin-Yih Hong, Chi-Ching Lai
  • Patent number: 9006039
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Publication number: 20140315944
    Abstract: The invention provides a chemical entity of Formula (I) wherein R1, R2, R3, Y, and n have any of the values described herein and compositions comprising such chemical entities; methods of making them; and their use in a wide range of methods, including metabolic and reaction kinetic studies, detection and imaging techniques, and radioactive treatments; and therapies, including inhibiting MAO, and MAO-B selectively, enhancing neuronal plasticity, treating neurological disorders, providing neuroprotection, treating a cognitive impairment associated with a CNS disorder, enhancing the efficiency of cognitive and motor training, providing neurorecovery and neurorehabilitation, enhancing the efficiency of non-human animal training protocols, and treating peripheral disorders (including obesity, diabetes, and cardiometabolic disorders) and their associated co-morbidities.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 23, 2014
    Inventors: Jillian Basinger, James Breitenbucher, Graeme Freestone, Varsha Gupta, Alan Kaplan, Chi-Ching Mak, Benjamin Pratt, Vincent Santora, Dipanjan Sengupta, Lino Valdez
  • Publication number: 20140315353
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant in the first openings; a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Publication number: 20140275548
    Abstract: The invention provides a chemical entity of Formula (I) wherein R1, R2, R3, Y, and n have any of the values described herein and compositions comprising such chemical entities; methods of making them; and their use in a wide range of methods, including metabolic and reaction kinetic studies, detection and imaging techniques, and radioactive treatments; and therapies, including inhibiting MAO, and MAO-B selectively, enhancing neuronal plasticity, treating neurological disorders, providing neuroprotection, treating a cognitive impairment associated with a CNS disorder, enhancing the efficiency of cognitive and motor training, providing neurorecovery and neurorehabilitation, enhancing the efficiency of non-human animal training protocols, and treating treating peripheral disorders (including obesity, diabetes, and cardiometabolic disorders) and their associated co-morbidities.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: Jillian Basinger, James Breitenbucher, Graeme Freestone, Varsha Gupta, Alan Kaplan, Chi-Ching Mak, Benjamin Pratt, Vincent Santora, Dipanjan Sengupta, Lino Valdez
  • Publication number: 20140273537
    Abstract: A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ching LO, Po-Hsiung LEU, Tzu-Chun LIN, Ding-I LIU, Jen-Chi CHANG, Ho-Ta CHUANG
  • Publication number: 20140280363
    Abstract: Methods, machines, and stored instructions are provided for determining hierarchical paths to nodes based on stored information about the nodes. A node analyzer analyzes a hierarchy to create mappings that represent the hierarchy. The mappings may include a “parent mapping” that maps selected-level nodes to parent nodes of the selected-level nodes, and a “path mapping” that maps a plurality of nodes other than the selected-level nodes to a plurality of paths, within the hierarchy, to the plurality of nodes. A path module then determines path(s) to specified node(s) at least in part by mapping the specified node(s) to particular parent node(s) of the specified node(s) using the parent mapping. The path module also maps the particular parent node(s) to particular path(s) using the path mapping. The information from the path and parent mappings may be assembled to form path(s) within the hierarchy to the specified node(s).
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Oracle International Corporation
    Inventors: LIJIE HENG, Chi Ching Chui, Yi Ouyang
  • Patent number: 8810045
    Abstract: A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 19, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 8749502
    Abstract: In view of existing mobile devices which have the limitation of relatively small area of the touch screen, the present invention describes a virtual touch sensing method based on computer vision technology. The method includes the steps of using more than one sensor to detect the coordinates of an indicator in a virtual touching area, and calculating the respective screen coordinates according to the coordinates of the indicator, where the area of the operation surface of the virtual touching area is independent to the area of the screen. The present invention also disclosed a corresponding virtual touch sensing system which provides a predictive control interface, where the area of the control interface is independent to the area of the actual screen.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: June 10, 2014
    Inventor: Chi Ching Lee
  • Publication number: 20130334694
    Abstract: A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability.
    Type: Application
    Filed: October 4, 2012
    Publication date: December 19, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 8604042
    Abstract: The invention provides biaryl meta-pyrimidine compounds having the general structure (A). The pyrimidine compounds of the invention are capable of inhibiting kinases, such as members of the Jak kinase family, and various other specific receptor and non-receptor kinases.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 10, 2013
    Assignee: TargeGen, Inc.
    Inventors: Glenn Noronha, Chi Ching Mak, Jianguo Cao, Joel Renick, Andrew McPherson, Binqi Zeng, Ved P. Pathak, Daniel L. Lohse, John D. Hood, Richard M. Soll
  • Publication number: 20130292832
    Abstract: A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer.
    Type: Application
    Filed: August 14, 2012
    Publication date: November 7, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu Tang, Chi-Ching Ho, Ying-Chou Tsai, Chang-Yi Lan
  • Publication number: 20130174747
    Abstract: A cooking appliance (2,20) comprises a first container (8, 26), a base (6, 44), an axle (10, 42) extending generally vertically from a bottom of the first container (8, 26), and a second container (12, 32) including a vertically extending funnel (34) which is engageable with a male member (46) arranged at an upper end of the axle (10, 42). The cooking appliance (2, 20) can assume a configuration in which the second container (12, 32) is rotatably drivenable by the male member (46) in relation to the first container (8, 26), to remove liquid from food contained in the second container (12, 32).
    Type: Application
    Filed: September 27, 2010
    Publication date: July 11, 2013
    Inventors: Pui Chi Ching, Ding Zheng Zhou, Wing Chung Lau, Wai Hing Lai
  • Patent number: 8481536
    Abstract: The invention provides benzotriazine compounds having formula (I). The benzotriazine compounds of the invention are capable of inhibiting kinases, such members of the Src kinase family, and various other specific receptor and non-receptor kinases.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 9, 2013
    Assignee: TargeGen, Inc.
    Inventors: Xianchang Gong, Kathy Barrett, Jianguo Cao, Colleen Gritzen, Glenn Noronha, John D. Hood, Chi Ching Mak, Andrew McPherson, Ved Prakash Pathak, Joel Renick, Richard M. Soll, Ute Splittgerber, Wolfgang Wrasidlo, Binqi Zeng, Ningning Zhao, Elena Dneprovskaia
  • Patent number: 8451617
    Abstract: An integrated circuit board includes a bridging filtering capacitor, a bypass capacitor, a thermistor, and a varistor. The integrated circuit board further includes an electrolytic capacitor set having a plurality of electrolytic capacitors, which are arranged in parallel and adjacent to each other, and a mounting frame for grouping the electrolytic capacitors. The present invention uses the above elements to reduce the vertical height, the horizontal width, and the occupied area. Therefore, the overall dimension of the circuit board can be reduced to make the electronic devices smaller, especially for thin electronic devices such as LCD TVs and screens.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: May 28, 2013
    Assignee: Lien Chang Electronic Enterprise Co., Ltd.
    Inventors: Chun-Kong Chan, Chi Ching Chen